Monolithic III-N and Si Transistor Integration on SOI
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Solution Overview
Problem
The integration of III-N transistors with silicon-based transistors is hindered by significant lattice and thermal expansion coefficient mismatches, limiting monolithic integration and scaling in semiconductor devices, despite the advantage of leveraging silicon fabrication infrastructure for economies of scale.
Innovation Solution
The use of a silicon-on-insulator (SOI) substrate for epitaxial growth of III-N and Si transistors, where a first silicon surface seeds the III-N semiconductor stack and a second surface seeds the raised silicon for Si FETs, with isolation dielectrics and metallization levels interconnecting the transistors to form monolithic or heterogeneous integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multi-chip integration approaches are used to integrate silicon-based devices with wurtzite semiconductor devices, then integration is achieved, but scaling and performance are limited
Solution Approach 1:
The patent merges silicon-based device fabrication with wurtzite semiconductor device fabrication into a single monolithic integration process. Multiple device types are integrated on a single substrate using compatible fabrication steps, eliminating the need for separate multi-chip assembly and enabling unified scaling across different device technologies.
Solution Approach 2:
The integration methodology creates a universal platform that can simultaneously fabricate silicon-based devices and wurtzite semiconductor devices using the same fabrication infrastructure. This multi-functional approach allows a single production line to handle multiple device types, improving both integration capability and scaling potential.
2Adaptability or versatility
If monolithic integration of silicon-based devices with wurtzite material system devices is attempted, then integration density is improved, but lattice mismatch and thermal expansion coefficient mismatch cause fabrication challenges
Solution Approach 1:
The patent applies local quality by using substrate-specific fabrication parameters for different device regions. Silicon-based devices are fabricated with silicon-optimized processes while wurtzite devices use wurtzite-optimized processes, allowing each material system to be manufactured under its ideal conditions while achieving high-density monolithic integration on a single substrate.
3Productivity
If III-N transistors are integrated into silicon fabrication infrastructure, then economies of scale are achieved, but lattice mismatch and thermal expansion coefficient mismatch remain challenges
Solution Approach 1:
The patent employs parameter changes by adjusting fabrication conditions such as temperature, pressure, and chemical composition to accommodate both silicon and III-N materials within the same fabrication infrastructure. This allows the existing silicon fabrication process to be adapted for III-N transistor production, achieving economies of scale while managing material compatibility through controlled parameter variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables effective monolithic or heterogeneous integration of III-N and Si transistors, overcoming lattice mismatch issues and facilitating high-performance semiconductor devices with improved electrical isolation and noise reduction, suitable for applications like power management ICs and RF power amplifiers.
Implementation Method 1
a first silicon surface seeds an epitaxial III-N semiconductor stack
Implementation Method 2
a second surface seeds an epitaxial raised silicon region
Data Source
AI summary
Methods and devices integrating circuitry including both III-N (e.g., GaN) transistors and Si-based (e.g., Si or SiGe) transistors. In some monolithic wafer-level integration embodiments, a silicon-on-insulator (SOI) substrate is employed as an epitaxial platform providing a first silicon surface advantageous for seeding an epitaxial III-N semiconductor stack upon which III-N transistors (e.g., III-N HFETs) are formed, and a second silicon surface advantageous for seeding an epitaxial raised silicon upon which Si-based transistors (e.g., Si FETs) are formed. In some heterogeneous wafer-level integration embodiments, an SOI substrate is employed for a layer transfer of silicon suitable for fabricating the Si-based transistors onto another substrate upon which III-N transistors have been formed. In some such embodiments, the silicon layer transfer is stacked upon a planar interlayer dielectric (ILD) disposed over one or more metallization level interconnecting a plurality of III-N HFETs into HFET circuitry.