Monolithic III-N Transistor and RF Filter Integration

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Solution Overview

Problem

The increasing complexity and cost of RF filters in mobile communication systems due to the growing number of bands and modes of communication, particularly with the advent of 5G, are exacerbated by the need for separate substrates for RF filters and III-N transistors, leading to increased RF losses and reduced performance.

Innovation Solution

Integrating III-N transistors with RF resonators on a single support structure, utilizing the sputtered piezoelectric material as a template for epitaxial growth, allowing for monolithic integration of all RF front-end components, eliminating the need for crystalline substrates and reducing RF losses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If separate substrates are used for RF filters and III-N transistors, then manufacturing processes can be optimized for each component independently, but RF losses increase and performance decreases due to additional interfaces and interconnects

Engineering Contradiction:
ImproveRF lossesVSAvoidintegration complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent merges RF filter resonators and III-N transistors onto a single substrate, eliminating separate substrates and interconnect interfaces. This integration reduces RF losses by removing additional signal paths and impedance discontinuities while consolidating manufacturing processes for both components on one substrate platform.

Inventive Principle:
Principle #5Merging (Combining)

2Area of stationary object

If multiple RF filters are integrated into a single IC, then the number of discrete components and IC area are reduced, but manufacturing precision requirements increase due to the need for precise resonator and transistor integration

Engineering Contradiction:
ImproveIC areaVSAvoidresonator integration precision
Core Design Contradiction:
Area of stationary objectVSManufacturing precision

Solution Approach 1:

The patent segments the substrate into distinct regions: a first region for RF filter resonators and a second region for III-N transistors. This spatial segmentation allows each component type to be optimized independently within its region while maintaining overall integration benefits, reducing the precision burden compared to fully intermixed layouts.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by providing different substrate regions with optimized characteristics for specific functions: the first region is optimized for resonator performance with appropriate piezoelectric layers, while the second region is optimized for transistor performance with suitable buffer layers and doping profiles, allowing each component to achieve its best performance locally.

Inventive Principle:
Principle #3Local quality

3Ease of manufacture

If sputtered piezoelectric material is used as a template for epitaxial growth, then monolithic integration is enabled and costs are reduced, but the complexity of the growth process increases

Engineering Contradiction:
Improvemanufacturing costVSAvoidepitaxial growth process complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by first depositing sputtered piezoelectric material layers (such as AlN) onto the substrate before performing epitaxial growth of III-N transistor structures. This pre-deposited layer serves as a prepared template that facilitates subsequent epitaxial growth, enabling monolithic integration while managing process complexity through staged fabrication.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This integration reduces costs and improves performance by minimizing RF losses and enabling a single-chip solution for RF filters, power amplifiers, switches, and low-noise amplifiers, thereby enhancing the efficiency and compactness of RF front-end components.

Implementation Method 1

a sputtered portion 148 of the piezoelectric material 128 is provided between a bottom electrode 152 and a top electrode 154

Methodology Applied
Scientific EffectSputtering: Sputtering

Implementation Method 2

an epitaxially grown piezoelectric III-N material 126 is provided between the sputtered portion 146 of the piezoelectric material 128 and the III-N channel material 112

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Implementation Method 3

a first portion 146 of the piezoelectric material 128 is provided between an III-N channel material 112 of the III-N transistor 102 and a support structure 108

Methodology Applied
Scientific EffectPiezoelectric effect: Piezoelectric Effect

Data Source

PatentUS11502124B2Filter-centric III-N films enabling RF filter integration with III-N transistors
Publication Date: 2022.11.15 INTEL CORP
  • US11502124B2 patent drawing
  • US11502124B2 patent drawing
  • US11502124B2 patent drawing

AI summary

Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same substrate or die as resonators of RF filters. An example IC structure includes a support structure (e.g., a substrate), a resonator, provided over a first portion of the support structure, and an III-N transistor, provided over a second portion of the support structure. The IC structure includes a piezoelectric material so that first and second electrodes of the resonator enclose a first portion of the piezoelectric material, while a second portion of the piezoelectric material is enclosed between the channel material of the III-N transistor and the support structure. In this manner, one or more resonators of an RF filter may be monolithically integrated with one or more III-N transistors. Such integration may reduce costs and improve performance by reducing RF losses incurred when power is routed off chip.