Monolithic Memory Accumulator Unit for System-on-Chip Initialization
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Solution Overview
Problem
Processing platforms, such as system-on-chips, often lack sufficient random access memory during initialization and production stages, limiting the execution of complex algorithms and requiring time-consuming Cache-as-RAM techniques that are not applicable when an L2 cache is absent or insufficient.
Innovation Solution
A processing device with a monolithic memory accumulator unit that utilizes idle storage capacity from integrated peripherals, converting virtual addresses to physical addresses to enable random access memory functionality, allowing the use of idle storage resources for data and instructions without impacting the peripherals' primary functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If Cache-as-RAM techniques are used to enable complex algorithms during initialization, then algorithm execution capability is improved, but device complexity increases and the solution becomes inapplicable when L2 cache is absent
Solution Approach 1:
The patent introduces a memory bridge as an intermediary component that translates access requests to peripheral storage resources, enabling random access memory functionality without modifying the processing device's logical structure. This mediator approach resolves the contradiction by providing algorithm execution capability while avoiding complex logical modifications to the processing device
Solution Approach 2:
The patent enables peripheral storage resources to serve dual purposes: their primary function for peripheral operation and secondary function as random access memory for algorithm execution. This multi-functionality allows the same storage resources to be used for both peripheral tasks and complex algorithm processing, improving versatility without adding dedicated memory hardware
2Quantity of substance
If random access memory capacity is increased to support user applications, then application capability is improved, but memory availability during production and testing stages deteriorates
Solution Approach 1:
The patent implements dynamic memory allocation where peripheral storage resources are allocated as random access memory only when peripherals are not actively serving their primary functions. During production and testing stages when peripherals are idle, their storage resources become available for algorithm execution. This dynamic sharing resolves the contradiction by making memory availability adaptive to operational context
Solution Approach 2:
The patent changes the operational state parameter of peripheral storage resources between 'peripheral mode' and 'memory mode' based on system needs. By controlling the operational state of peripherals, the same storage resources can provide different functions at different times, increasing both effective memory capacity and availability across operation stages
3Quantity of substance
If L2 cache is used for random access memory functionality, then memory capability is improved, but the solution becomes inapplicable when L2 cache is absent or insufficient
Solution Approach 1:
The patent creates a universal memory solution that works with any processing platform regardless of whether it has L2 cache. By using peripheral storage resources with memory bridge translation, the system provides random access memory functionality that is independent of the presence or size of L2 cache, thereby improving compatibility across different processing platforms
Solution Approach 2:
The patent effectively creates a virtual random access memory layer that copies the functionality of physical L2 cache by translating access requests to peripheral storage. This virtual memory copy allows systems without L2 cache to access complex algorithms during initialization, providing universal compatibility while maintaining the desired memory capability
Data Source
AI summary
A processing device comprises inter alia a monolithic memory accumulator unit, which exposes a virtual memory space to an interconnect bus and comprises a conversion table with translation information to translate requests with virtual addresses into requests with physical addresses. The MMA is configured to receive a transaction request; to translate the address of the received request into physical address(es); and to pass on transaction request(s) to storage locations of an integrated peripheral.A processing device comprises at least one integrated peripheral, IP, with an accessibility adapter unit, AA, which exposes a virtual memory space to the interconnect bus 650 and which comprises a conversion table with translation information. The AA 150 is configured to receive a transaction request; to translate the address of the received request into physical address(es); and to route transaction request(s) to storage locations of the IP.