Monolithic Memory Stack With Shared CMOS for High-Bandwidth Density
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Solution Overview
Problem
Legacy microelectronic packages face challenges in achieving high-bandwidth and high-density memory integration with CPUs or GPUs due to the separate processing of DRAM and eDRAM on different wafers, leading to increased costs and performance issues.
Innovation Solution
Integrating DRAM and eDRAM in a monolithic stack within a wafer 3D stacked form, sharing the CMOS periphery, which allows for improved latency, bandwidth, and density while reducing manufacturing complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If DRAM and eDRAM are processed on different wafers in legacy packages, then manufacturing flexibility is maintained, but integration complexity and cost increase
Solution Approach 1:
The patent merges DRAM and eDRAM processing into a single monolithic wafer, eliminating the need for separate wafer processing and integration. This combining of previously separate manufacturing processes reduces both manufacturing complexity and integration complexity while improving memory performance and density.
Solution Approach 2:
The monolithic wafer structure enables a single substrate to host multiple memory types (DRAM and eDRAM) along with CMOS periphery circuits, replacing the need for multiple specialized wafers. This multi-functional approach simplifies the overall manufacturing process while maintaining design flexibility.
2Quantity of substance
If DRAM and eDRAM are integrated in a monolithic stack, then memory density and bandwidth increase, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from planar memory integration to a three-dimensional stacked architecture, where DRAM and eDRAM layers are vertically stacked within the monolithic wafer. This vertical stacking increases memory density without proportionally increasing manufacturing precision requirements, as the stacking leverages existing 3D integration capabilities.
Solution Approach 2:
The monolithic stack embeds multiple memory layers (DRAM and eDRAM) within a single wafer structure, with each memory type nested in specific layers. This nesting approach allows high memory density to be achieved while utilizing standard monolithic fabrication processes, avoiding the need for significantly enhanced manufacturing precision.
3Reliability
If separate wafer processing is used for DRAM and eDRAM, then process optimization for each memory type is maintained, but latency and bandwidth performance deteriorate
Solution Approach 1:
By combining DRAM and eDRAM into a monolithic wafer structure with shared CMOS periphery, the patent enables faster data access and lower latency compared to separate wafer architectures. The integrated design allows for optimized signal paths and reduced inter-wafer communication delays, improving overall memory performance.
Solution Approach 2:
The shared CMOS periphery acts as an intermediary that coordinates access to both DRAM and eDRAM layers within the monolithic stack. This unified control mechanism optimizes memory operations, reducing latency by eliminating the need for separate control circuits and inter-wafer signaling that would otherwise increase access time.
Data Source
AI summary
Embodiments may relate to a microelectronic package that includes a first plurality of memory cells of a first type coupled with a substrate. The microelectronic package may further include a second plurality of memory cells of a second type communicatively coupled with the substrate such that the first plurality of memory cells is between the substrate and the second plurality of memory cells. Other embodiments may be described or claimed.