Semiconductor device and method of fabricating a semiconductor device

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Solution Overview

Problem

Existing power transistor devices for power electronic applications, such as Si CoolMOS®, Si Power MOSFETs, and Si Insulated Gate Bipolar Transistors (IGBTs), are large in size and have significant electrical connections that lead to losses and reduced efficiency in circuits like half-bridge circuits.

Innovation Solution

A semiconductor device is developed with a vertical power FET and a lateral FET monolithically integrated into a semiconductor substrate, where the lateral FET is coupled to the gate of the vertical FET, reducing physical size and electrical connections, and incorporating a charge compensation structure to enhance efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If separate packaged components are used for power MOSFETs and gate driver, then individual component performance can be optimized, but the overall circuit size increases and electrical connection losses increase

Engineering Contradiction:

Improveelectrical connection lossesVSAvoidcircuit structure

Core Design Contradiction:

Loss of energyVSDevice complexity

Solution Approach 1:

The patent merges the power MOSFET and gate driver into a single monolithic integrated circuit. The gate driver transistor and power MOSFET are fabricated on the same semiconductor substrate, eliminating the need for separate packaged components and reducing electrical connection losses between them.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The semiconductor substrate serves multiple functions simultaneously: it acts as the body for both the gate driver transistor and the power MOSFET, provides electrical connections, and integrates the drift region. This multi-functionality reduces the overall device complexity while maintaining performance.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Area of stationary object

If separate packaged components are mounted within a module, then individual components can be independently optimized, but the overall module size increases

Engineering Contradiction:

Improvecircuit sizeVSAvoidintegration process

Core Design Contradiction:

Area of stationary objectVSEase of manufacture

Solution Approach 1:

The patent combines the gate driver and power MOSFET into a single monolithic integrated circuit structure, dramatically reducing the overall circuit area. Both transistors are fabricated on the same semiconductor substrate using standard CMOS or bipolar process techniques, simplifying the manufacturing process.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent utilizes the vertical dimension of the semiconductor substrate by implementing a drift region that extends from the surface into the substrate. This three-dimensional structure allows for high-voltage operation while maintaining a compact planar footprint, effectively reducing the circuit area.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12550422B2Semiconductor device and method of fabricating a semiconductor device

Publication Date: 2026.02.10 INFINEON TECH AUSTRIA AG

AI summary

In an embodiment, a semiconductor device is provided that includes: a vertical power FET configured to switch a load current and provide a channel of a first conductivity type; and a lateral FET configured to drive the vertical power FET and provide a channel of a second conductivity type opposing the first conductivity type. The vertical power FET and the lateral FET are monolithically integrated into a semiconductor substrate of the first conductivity type and a drain of the lateral FET is electrically coupled to a gate of the vertical power FET.