Monolithic Power MOSFET Gate Driver Integration for Lower Connection Loss
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Solution Overview
Problem
Existing power transistor devices for power electronic applications, such as Si CoolMOS®, Si Power MOSFETs, and Si Insulated Gate Bipolar Transistors (IGBTs), are large in size and have significant electrical connections that lead to losses and reduced efficiency.
Innovation Solution
A semiconductor device is developed with a vertical power FET and two lateral FETs monolithically integrated into a semiconductor substrate, where the lateral FETs form an output stage of the gate driver circuit, reducing physical size and electrical connections, and incorporating a charge compensation structure to enhance efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If separate packaged components are used for power MOSFETs and gate driver, then device functionality is achieved, but circuit size is large and efficiency is reduced due to significant electrical connections
Solution Approach 1:
The patent merges the power MOSFET and gate driver components into a single monolithic semiconductor device. The gate driver circuitry is integrated directly onto the same semiconductor substrate as the power MOSFET, eliminating the need for separate packaged components and reducing electrical connection losses between components.
Solution Approach 2:
The patent transitions from a three-dimensional assembly of separate packaged components to a two-dimensional planar integration on a single semiconductor substrate. This dimensional change enables direct integration of the gate driver circuitry with the power MOSFET, reducing connection path lengths and energy losses.
2Area of stationary object
If separate packaged components are mounted within a module, then device functionality is achieved, but physical size of the circuit is reduced only partially
Solution Approach 1:
The patent combines multiple functional components (power MOSFET, gate driver, and associated circuitry) into a single monolithic device structure. This merging eliminates the need for mounting separate components within a module, thereby minimizing both the physical footprint and electrical connection path lengths.
Solution Approach 2:
The patent segments the semiconductor substrate into distinct functional regions: a first region for the power MOSFET and a second region for the gate driver circuitry. This segmentation allows for optimized layout and minimization of electrical connections while maintaining functional separation.
3Productivity
If vertical power FET with lateral FETs are monolithically integrated, then efficiency is improved and circuit size is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent divides the semiconductor substrate into distinct functional regions: a first region for the vertical power MOSFET and a second region for the lateral FETs forming the gate driver output stage. This segmentation simplifies the fabrication process by allowing standardized manufacturing techniques to be applied to each region while achieving high integration density.
Solution Approach 2:
The patent uses a common semiconductor substrate for both the power MOSFET and gate driver circuitry, making the substrate serve multiple functions. This universal approach reduces manufacturing steps compared to processing separate substrates and then assembling them, thereby improving ease of manufacture despite the integrated design.
Data Source
AI summary
In an embodiment, a semiconductor device includes a vertical power FET for switching a load current, the power FET including a channel region of a first conductivity type and a first lateral FET and a second lateral FET providing an output stage of gate driver circuitry for driving the power FET. The first lateral FET includes a channel region of the first conductivity type and the second lateral FET includes a channel region of a second conductivity type opposing the first conductivity type. The power FET and the first and second lateral FETs are monolithically integrated into a semiconductor substrate of the first conductivity type and that has a first surface. A drain of the first lateral FET and a source of the second lateral FET are electrically coupled to a gate of the power FET.