Monolithic Multi-FET Layout With Shared Source-Drain Regions
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Solution Overview
Problem
Conventional power transistors are large and inefficient, limiting power distribution and heating in electronic systems due to resistive losses and parasitic capacitance and inductance, necessitating improved power transistor designs for reduced size and enhanced performance.
Innovation Solution
A monolithic multi-FET transistor structure comprising a semiconductor substrate with a bulk layer, dielectric layer, and epitaxial layer, where the epitaxial layer is patterned with isolation structures to divide the multi-FET area into separate FET portions, sharing common sources or drains to reduce area and increase integration, and connected via more conductive contacts to minimize resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional power transistors are individually packaged with heat sinks, then they can handle large currents and voltages, but they become relatively large in size compared to logic circuits
Solution Approach 1:
Multiple FETs are integrated onto a single semiconductor substrate to form a monolithic multi-FET transistor device, combining multiple power handling units into one compact structure that replaces several individual packaged transistors
Solution Approach 2:
The patent transitions from two-dimensional planar FET structures to three-dimensional vertically stacked FET configurations, allowing multiple FETs to be stacked along the vertical axis to increase power density without increasing footprint area
2Loss of energy
If higher voltages are provided to mitigate resistive losses, then power delivery efficiency improves, but the size and efficiency of the power transistor becomes more critical
Solution Approach 1:
The power transistor is segmented into multiple FET units with shared sources and drains, where each FET can be independently controlled to optimize power delivery at different voltage levels and reduce overall resistive losses through parallel current paths
Solution Approach 2:
The monolithic multi-FET structure provides multiple functions within a single device, including high-voltage power switching, low-voltage logic control integration, and configurable parallel/series arrangements to adapt to different power delivery requirements
3Productivity
If multiple separate FETs are integrated on a single substrate, then device density increases, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into modular stages: forming common source/drain regions, creating isolation structures, depositing gate dielectrics and gates, and forming contacts, allowing systematic fabrication of complex multi-FET structures
Solution Approach 2:
Multiple FETs share common source and drain regions, reducing the total number of discrete regions that need to be formed and processed, thereby simplifying manufacturing while increasing device density
Data Source
AI summary
A monolithic multi-FET transistor comprises an epitaxial layer disposed on a dielectric layer. The epitaxial layer comprises a crystalline semiconductor material and a multi-FET area. An isolation structure surrounds the multi-FET area and divides the multi-FET area into separate FET portions. A gate disposed on a gate dielectric extends over each FET portion. A source and a drain are each disposed on opposite sides of the gate on the epitaxial layer within each FET portion. Each gate, source, and drain comprise a separate electrical conductor and the gate, source, drain, and epitaxial layer within each FET portion form a field-effect transistor. Gate, source, and drain contacts electrically connect the gates, sources, and drains of the separate FET portions, respectively. At least the sources or drains of two neighboring FET portions are disposed in common over at least a portion of the isolation structure dividing the two neighboring FET portions.