Monolithic NAND-NOR Memory Device Architecture
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Solution Overview
Problem
Current NAND flash memory architectures face limitations in random access time and efficiency due to their design, which hinders their ability to perform code execution and other high-speed data operations, and they require multiple memory technologies in a single package, leading to compatibility and cost issues.
Innovation Solution
A monolithic semiconductor memory device with a NAND architecture is developed, featuring a matrix divided into fast and slow portions with shared bit lines and decoupled operation, utilizing strap techniques to reduce propagation times and improve conductivity, allowing for efficient data storage and code execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NAND architecture is used for high density and low power consumption, then data storage capacity and power efficiency are improved, but random access time deteriorates
Solution Approach 1:
The memory device is divided into two distinct memory portions: a first memory portion with NOR architecture optimized for fast random access, and a second memory portion with NAND architecture optimized for high density data storage. This segmentation allows each portion to specialize in its respective strength, resolving the contradiction between fast access and high capacity.
Solution Approach 2:
Different architectural qualities are applied to different portions of the memory device. The first portion uses NOR architecture with local optimization for random access operations, while the second portion uses NAND architecture with local optimization for sequential access and storage capacity, allowing each region to have the quality best suited for its function.
2Adaptability or versatility
If multiple memory technologies are integrated in a single package to meet diverse needs, then functionality is improved, but device complexity and compatibility issues worsen
Solution Approach 1:
Two different memory architectures (NOR and NAND) are merged into a single monolithic integrated circuit on one semiconductor chip. This combining provides the versatility of multiple memory types while avoiding the complexity of multi-chip packages, as both memory portions share common circuitry and control logic.
Solution Approach 2:
The memory device provides universal functionality by implementing both NOR and NAND memory portions that can be accessed through a unified interface. The control circuitry automatically routes operations to the appropriate memory portion based on the operation type, providing multi-functionality without requiring separate control mechanisms for each memory type.
3Productivity
If NAND architecture is used for high write/erase speed, then programming performance is improved, but random access efficiency deteriorates
Solution Approach 1:
The memory device is divided into two distinct memory portions: a first memory portion with NOR architecture optimized for fast random access, and a second memory portion with NAND architecture optimized for high density data storage. This segmentation allows each portion to specialize in its respective strength, resolving the contradiction between fast access and high capacity.
Data Source
AI summary
A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.