Monolithic III-Nitride Power Converter Parasitic Impedance Reduction
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Solution Overview
Problem
Integrated circuits with silicon devices face challenges in integrating high voltage and low voltage devices and their drivers due to layout limitations, leading to long and non-linear connections that introduce parasitic impedances, making it difficult to achieve efficient and compact power management solutions for applications like buck converters.
Innovation Solution
A III-nitride-based power stage is integrated directly with the load, using III-nitride power switches and predrivers, and optionally passive components, to minimize parasitic inductances and resistances, allowing for a compact and efficient power management solution by reducing wirebonds and optimizing layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon devices are used for integrated circuits, then manufacturing maturity and device availability are improved, but parasitic impedances increase due to long and non-linear connections between power devices and drivers
Solution Approach 1:
The patent merges the power stage and driver stage into a single integrated circuit chip, eliminating the need for separate packages and long interconnections. This integration directly reduces parasitic inductance and resistance by placing the driver circuitry in immediate proximity to the power devices, while still utilizing mature silicon manufacturing processes.
Solution Approach 2:
The patent transitions from a three-dimensional packaged approach with wire bonds to a planar integrated circuit layout where power devices and drivers are arranged on the same chip surface. This dimensional change allows for optimized signal paths and minimizes connection length, reducing parasitic effects.
2Area of stationary object
If power devices and drivers are integrated in a single silicon die, then area occupancy is improved, but layout limitations cause long and non-linear connections introducing parasitics
Solution Approach 1:
The patent applies local quality by creating dedicated regions on the chip for power devices and driver circuits, with optimized local interconnections. The layout strategically places high-current paths and control signal paths in separate regions to minimize interference and parasitic coupling, while maintaining compact overall area.
Solution Approach 2:
The integrated circuit is segmented into distinct functional blocks (power stage, driver stage, control logic) that are independently optimized and then integrated. This segmentation allows for optimized routing within each block and minimizes the length of inter-block connections, reducing parasitic inductance while maintaining compact area.
3Power
If conventional power devices are used, then power delivery capability is improved, but thermal load increases due to heat generation during operation
Solution Approach 1:
The patent introduces an intermediary integrated circuit architecture that sits between the power source and the load, incorporating efficient power management functions. This intermediary structure enables better thermal management through integrated voltage regulation and power switching, reducing overall system thermal load while maintaining power delivery capability.
Data Source
AI summary
A power arrangement that includes a monolithically integrated III-nitride power stage having III-nitride power switches and III-nitride driver switches.