Monolithic Non-Volatile Memory Device with Direct PCIe Interface
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Solution Overview
Problem
The existing memory systems require a separate controller for interfacing between the host device and memory chips, which leads to increased processing bandwidth consumption, slower data transmission, and higher costs, especially in single memory chip configurations with lower memory capacities.
Innovation Solution
A monolithic non-volatile memory device with a direct PCIe interface eliminates the need for a separate controller by enabling direct communication between the host device and the memory chip, reducing the number of command translations and simplifying the system architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a separate controller is used for interfacing between host device and memory chips, then the memory system can be designed with modular architecture, but processing bandwidth consumption increases and data transmission speed decreases
Solution Approach 1:
The patent merges the controller functionality directly into the memory chip by implementing a PCIe interface within the memory device itself. This integration eliminates the need for a separate controller, allowing the memory chip to directly communicate with the host device through the PCIe bus, thereby reducing processing bandwidth consumption and increasing data transmission speed while maintaining modular architecture through the standardized PCIe interface
2Adaptability or versatility
If a separate controller is used for interfacing between host device and memory chips, then command translation can be performed, but system cost increases especially in single memory chip configurations
Solution Approach 1:
The controller functionality is merged directly into the memory chip by integrating the PCIe interface and command translation capabilities within the memory device. This eliminates the need for a separate controller component, reducing system cost particularly in single memory chip configurations while maintaining the ability to perform command translation and interface with various host devices through the standardized PCIe protocol
Solution Approach 2:
The memory chip is designed with universal PCIe interface capabilities that allow it to function as both the storage device and the controller. The integrated PCIe interface enables the memory chip to directly communicate with host devices, perform command translation, and interface with various computing platforms, eliminating the need for separate controller components and reducing overall system cost
3Ease of operation
If a separate controller is used for interfacing between host device and memory chips, then memory access can be managed, but boot time increases
Solution Approach 1:
The controller functionality is merged directly into the memory chip by integrating the PCIe interface and memory access management capabilities within the memory device. This integration eliminates the need for a separate controller, allowing for faster boot times as the memory chip can directly respond to host device commands without the additional translation and processing steps required by a separate controller, while maintaining effective memory access management through the integrated design
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances data throughput, reduces system costs, and accelerates boot times by eliminating the separate controller, allowing for faster and more efficient data access and processing.
Implementation Method 1
applying a high positive voltage, which may be referred to as a 'program voltage,' a 'programming power voltage,' or 'VPP,' to a control gate to generate Fowler-Nordheim tunneling (referred to as 'F-N tunneling') between a floating gate and the semiconductor substrate. When F-N tunneling is occurring, electrons of the bulk area are accumulated on the floating gate by an electric field of VPP applied to the control gate to increase a threshold voltage of the memory cell
Implementation Method 2
An erasing operation of the memory cell is concurrently performed in units of sectors sharing the bulk area (referred to as 'blocks'), by applying a high negative voltage, which may be referred to as an 'erase voltage' or 'Vera,' to the control gate and a configured voltage to the bulk area to generate the F-N tunneling. In this case, electrons accumulated on the floating gate are discharged into the source area, so that the memory cells have an erasing threshold voltage distribution
Data Source
AI summary
An embedded system includes a host device that includes a first peripheral component interconnect express (PCIe) interface; a non-volatile memory (NVM) device that includes a second PCIe interface; and a PCIe bus directly coupled to the first PCIe interface and the second PCIe interface for transmitting direct communications between the host device and the monolithic NVM device.