Monolithically Integrated Absolute Pressure Sensor
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional MEMS devices face challenges in increasing performance, reducing size, and decreasing cost, while also requiring more complex microsystems with greater computational power, which are not adequately addressed by existing technologies.
Innovation Solution
The development of monolithically integrated absolute pressure sensors using IC foundry-compatible processes, where a CMOS substrate is fabricated with a diaphragm formed from single crystalline silicon material, and capacitive or piezoresistive pressure sensors are created through fusion or eutectic bonding, allowing for smaller die sizes and lower parasitic capacitance without significant modifications to conventional equipment and processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional MEMS fabrication processes are used, then manufacturing simplicity is maintained, but device performance and integration capability are limited
Solution Approach 1:
The patent merges MEMS fabrication with standard CMOS IC fabrication processes, allowing pressure sensors to be manufactured using the same semiconductor manufacturing infrastructure. This integration enables the use of proven CMOS processes for creating diaphragms, sensing elements, and electronic circuitry on a single chip, thereby improving device performance while managing fabrication complexity through process standardization.
Solution Approach 2:
The invention creates a universal fabrication platform that can produce both CMOS electronic circuits and MEMS pressure sensing elements using the same process steps. The CMOS-compatible approach allows a single fabrication line to manufacture multiple device types (sensors, signal conditioning circuits, processing units) with different functions, enhancing overall system capability without requiring separate specialized manufacturing processes.
2Area of moving object
If MEMS and CMOS are integrated on a single chip, then die size is reduced, but parasitic capacitance increases
Solution Approach 1:
The patent applies local quality by implementing shielding structures and grounding schemes specifically in regions where parasitic capacitance becomes problematic. The CMOS process allows for localized addition of guard rings, shielding layers, and optimized trace routing near the pressure sensing diaphragm to minimize parasitic effects in critical areas while maintaining compact overall device dimensions.
Solution Approach 2:
The invention replaces mechanical isolation approaches with electrical compensation techniques enabled by CMOS integration. Instead of physically isolating the sensing element to reduce parasitic capacitance, the design uses CMOS circuitry to detect and compensate for parasitic effects through differential measurements and signal processing, thereby maintaining small die size while managing capacitance issues through electronic means.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables structural flexibility and integration of MEMS and CMOS on a single chip, achieving smaller die sizes and lower parasitic capacitance, while being compatible with conventional semiconductor and MEMS process technologies, thus enhancing the performance and efficiency of MEMS devices.
Implementation Method 1
The bonding process can include a fusion bonding or eutectic bonding process
Implementation Method 2
The bonding process can include a fusion bonding or eutectic bonding process
Implementation Method 3
At least one capacitive or piezoresistive pressure sensors can be formed
Implementation Method 4
At least one capacitive or piezoresistive pressure sensors can be formed
Data Source
AI summary
An integrated pressure sensing device and method of fabrication thereof are disclosed. The method can include providing a substrate member having a surface region and forming a CMOS IC layer overlying the substrate and forming an oxide layer overlying the CMOS IC layer. A portion of the oxide layer can be removed to form a cavity region. A single crystalline silicon wafer can be bonded overlying the oxide surface region to seal the cavity region. The bonding process can include a fusion bonding or eutectic bonding process. The wafer can be thinned to a desired thickness and portions can be removed and filled with metal materials to form via structures. A pressure sensor device can be formed from the wafer, and can be co-fabricated with another sensor from the wafer. The pressure sensor and the other sensor can share a cavity pressure or have separate cavity pressures.