Monolithic Resistive Memory Integration via CMOS Foundry Compatible Processes

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Solution Overview

Problem

Resistive memory integration faces challenges such as thermal budget constraints and plasma damage, which complicate the monolithic integration with CMOS circuitry, and existing backend of line processes require significant changes to accommodate resistive memory fabrication.

Innovation Solution

The integration of resistive memory devices using integrated-circuit foundry compatible processes, where the memory device is fabricated within a thermal budget of CMOS devices and using existing backend of line processes, maintaining the inter-layer dielectric thickness and avoiding changes in RC delays, thus allowing for simpler and cost-effective monolithic integration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If resistive memory is integrated using existing backend of line processes, then manufacturing complexity is reduced, but thermal budget constraints and plasma damage complicate the integration

Engineering Contradiction:

Improveintegration process complexityVSAvoidplasma damage and thermal budget constraints

Core Design Contradiction:

Device complexityVSObject-affected harmful factors

Solution Approach 1:

The patent segments the resistive memory fabrication into distinct stages: forming the memory stack structure first, then selectively removing portions to create the final device. This segmentation allows each stage to be optimized independently, reducing overall process complexity while managing thermal and plasma exposure at each step

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by pre-forming the memory stack structure with all necessary layers (conductive layers, insulating layers, sacrificial layers) before final device formation. This preliminary structuring allows subsequent plasma and thermal processes to be more controlled and targeted, reducing harmful effects

Inventive Principle:

Principle #10Preliminary action

2Adaptability or versatility

If significant changes are made to backend of line processes to accommodate resistive memory fabrication, then resistive memory can be integrated, but manufacturing cost and process complexity increase

Engineering Contradiction:

Improveresistive memory integration capabilityVSAvoidmanufacturing cost and process simplicity

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent designs the memory stack structure to be compatible with existing backend of line process tools and methodologies. The same deposition, etching, and planarization tools used for CMOS fabrication are utilized for resistive memory fabrication, eliminating the need for specialized equipment and reducing manufacturing costs

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent adjusts process parameters (temperature, pressure, material compositions) within the existing backend process windows to accommodate resistive memory fabrication. By staying within established parameter ranges, the patent avoids significant process changes while achieving successful integration

Inventive Principle:

Principle #35Parameter changes

3Adaptability or versatility

If inter-layer dielectric thickness is changed to accommodate resistive memory structure, then resistive memory can be formed, but RC delays change affecting circuit performance

Engineering Contradiction:

Improveresistive memory structure formationVSAvoidcircuit performance and RC delay stability

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent embeds the resistive memory structure within the existing inter-layer dielectric framework. The memory stack is formed within designated regions without disrupting the overall dielectric layer architecture, ensuring that RC delay characteristics remain consistent with original circuit designs

Inventive Principle:

Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent applies local modifications only where resistive memory structures are formed, while maintaining the original inter-layer dielectric thickness and properties in other regions. This localized approach preserves circuit performance characteristics while enabling memory integration

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS10096653B2Monolithically integrated resistive memory using integrated-circuit foundry compatible processes

Publication Date: 2018.10.09 CROSSBAR INC

AI summary

Provided is a monolithic integration of resistive memory with complementary metal oxide semiconductor using integrated circuit foundry processes. A memory device is provided that includes a substrate comprising one or more complementary metal-oxide semiconductor devices, a first insulator layer formed on the substrate; and a monolithic stack. The monolithic stack includes multiple layers fabricated as part of a monolithic process over the first insulator layer. The multiple layers include a first metal layer, a second insulator layer, and a second metal layer. A resistive memory device structure is formed within the second insulator layer and within a thermal budget of the one or more complementary metal-oxide semiconductor devices. The resistive memory device structure is implemented as a pillar device or as a via device. Further, the first metal layer is coupled to the second metal layer.