Monolithic SAW Multiplexer Layout for Heat and Size Constraints
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Solution Overview
Problem
Current multiplexers using discrete electroacoustic components with multiple filter functions face challenges such as large size, suboptimal heat dissipation, thermal sensitivity, and difficulty in optimizing different filter functions on a single chip, leading to increased material loss and mechanical instability.
Innovation Solution
A multiplexer is designed as a single monolithic stack with a Si carrier substrate, thin film piezoelectric layer, and dielectric layer, incorporating SAW filter circuits and a package with a cavity to enclose SAW resonators, utilizing materials with high thermal conductivity and allowing flexible placement of resonators for improved heat dissipation and reduced chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If discrete electroacoustic components with multiple filter functions are used, then each filter function can be separately optimized, but the device size increases and heat dissipation becomes suboptimal
Solution Approach 1:
The patent combines multiple discrete electroacoustic filter components onto a single carrier substrate, integrating multiple filter functions (e.g., SAW, BAW, FBAR filters) into one unified device. This merging approach reduces the overall device area while maintaining the ability to separately optimize each filter function through dedicated design spaces on the same substrate.
Solution Approach 2:
The carrier substrate is designed as a universal platform that can accommodate different types of electroacoustic filters (SAW, BAW, FBAR) with different layer stacks and configurations. This multi-functional substrate allows various filter technologies to coexist and be independently optimized while sharing common infrastructure elements.
2Reliability
If discrete electroacoustic components are used, then individual filter failure does not affect other filters, but the carrier board must be large and heat dissipation is suboptimal
Solution Approach 1:
The carrier substrate incorporates localized thermal management features such as heat sinks, thermal vias, and conductive pathways positioned specifically under or near each filter component. This local quality approach optimizes heat dissipation for each individual filter while maintaining the overall compact structure, preventing thermal buildup that would occur in larger distributed configurations.
3Loss of substance
If larger chips with multiple filter functions are used, then wafer material usage is reduced, but the device becomes more sensitive to cracks and thermal mismatch
Solution Approach 1:
While integrating multiple filters on a single chip to reduce wafer material usage, the patent segments the chip into distinct functional regions with isolated stress zones. Each filter type has its own optimized layer stack and mounting structure that can independently accommodate thermal expansion differences, reducing the propagation of cracks and thermal mismatch effects across the entire device.
4Area of stationary object
If multiple filter functions are combined on a single chip, then device size is reduced, but optimizing different filter functions simultaneously becomes difficult
Solution Approach 1:
The carrier substrate provides locally optimized environments for each filter type, with dedicated interlayer structures, electrode configurations, and material compositions tailored to specific filter requirements. This allows each filter function to be optimized independently for its performance characteristics while maintaining compact integration, reducing the complexity of simultaneous optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces wafer material usage, enhances heat dissipation, and allows precise trimming of filter circuits, resulting in a smaller, more stable, and efficient multiplexer with improved thermal matching and reduced production costs.
Implementation Method 1
a thin film piezoelectric layer above the substrate
Implementation Method 2
three SAW filter circuits, Each of the filter circuits comprises a series signal line and a number of SAW resonators
Data Source
AI summary
At least three acoustic filters circuits FC are arranged on a single chip CH. At least two of them are electrically connected already on the chip for multiplexing. This reduces space consumption and leads to smaller device size.