Monolithic Semiconductor Chip Design Eliminates Tunnel Junction Ohmic Losses
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Solution Overview
Problem
Radiation-emitting semiconductor chips face efficiency drops with increasing current density, leading to reduced brightness and elevated operating voltage due to ohmic losses at tunnel junctions and internal absorption, which are inherent in stacked semiconductor chips.
Innovation Solution
An optoelectronic semiconductor chip design featuring two monolithically integrated semiconductor layer sequences with a common second semiconductor region, eliminating the need for tunnel junctions or bonding layers, and utilizing a dielectric mirror for current spreading, which allows for low current density operation and enhanced radiation efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If semiconductor chips are stacked vertically with tunnel junctions to achieve high radiances, then brightness per area is improved, but ohmic losses at tunnel junctions increase operating voltage
Solution Approach 1:
The patent extracts and eliminates the tunnel junction component from the stacked semiconductor chip structure. By directly monolithically integrating the semiconductor layer sequences without tunnel junctions, the invention removes the source of ohmic losses while maintaining the vertical stacking configuration for high radiance
Solution Approach 2:
The patent merges the semiconductor layer sequences directly into a monolithic structure where the second semiconductor region of one sequence becomes the first semiconductor region of the next sequence. This direct merging eliminates the need for separate tunnel junction layers and their associated ohmic losses
2Reliability
If dopant concentrations are increased to compensate for high activation energy in large band gap semiconductors, then charge carrier density is improved, but ohmic losses at tunnel junctions increase
Solution Approach 1:
The invention extracts and removes the tunnel junction structure that causes ohmic losses. By eliminating this component, the patent avoids the energy losses associated with high dopant concentrations and high activation energy materials, while maintaining reliable charge carrier density through direct monolithic integration
3Illumination intensity
If vertically stacked semiconductor chips are used to achieve high radiances, then brightness is improved, but internal absorption impairs radiation efficiency
Solution Approach 1:
The patent changes the structural parameters of the stacked semiconductor chips by eliminating tunnel junctions and bonding layers. This parameter change reduces internal absorption paths and improves radiation efficiency while maintaining the vertical stacking configuration for high radiance output
4Stability of the object's composition
If tunnel junctions are integrated into the semiconductor chip to connect stacked layers, then structural connection is improved, but ohmic losses increase operating voltage
Solution Approach 1:
The patent merges adjacent semiconductor layer sequences directly into a continuous monolithic structure. The second semiconductor region of one layer sequence becomes the first semiconductor region of the next sequence, providing structural connection without requiring separate tunnel junction components and their associated ohmic losses
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves high radiance without ohmic losses, reduces current crowding, and simplifies epitaxy structures, while enabling efficient radiation outcoupling and reduced contact surface area, thereby improving overall chip performance.
Implementation Method 1
a first active zone arranged between the first semiconductor region and the second semiconductor region for generating a first electromagnetic radiation
Implementation Method 2
utilizing a dielectric mirror for current spreading
Implementation Method 3
The layers of the layer stack are preferably monolithically integrated. The layers are then grown epitaxially above one another
Data Source
AI summary
A semiconductor chip with a layer stack includes a first semiconductor layer sequence and a second semiconductor layer sequence. The first semiconductor layer sequence includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type and an active zone arranged therebetween. The second semiconductor layer sequence includes the second semiconductor region of the second conductivity type, a third semiconductor region of the first conductivity type and a second active zone arranged therebetween.