Monolithic Semiconductor Switches Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a need to increase the integration level of field effect transistors (FETs) in semiconductor devices while maintaining appropriate device characteristics, particularly in half-bridge configurations used in applications like motor drivers and DC-converters, where existing technologies face challenges in optimizing the integration of high-side and low-side switches.
Innovation Solution
The integration of monolithic semiconductor switches within a single semiconductor die, where one FET is configured as a high-side switch and another as a low-side switch, with specific electrical coupling and separation of contact areas to enhance the half-bridge configuration, allowing for improved integration and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple FETs are integrated on a single semiconductor die to increase integration level, then device complexity increases, but manufacturing precision and device characteristics may deteriorate
Solution Approach 1:
The patent divides the semiconductor die into distinct regions with different epitaxial layers - a first region with a first epitaxial layer for one FET and a second region with a second epitaxial layer for another FET. This segmentation allows each FET to be optimized independently while maintaining high integration level on the single die, thus resolving the contradiction between increased integration and maintained manufacturing precision.
2Adaptability or versatility
If high-side and low-side switches are integrated in half-bridge configuration, then device functionality is improved, but electrical coupling and separation requirements increase complexity
Solution Approach 1:
The patent merges the electrical coupling function into the common substrate structure, where both high-side and low-side switches share the same semiconductor die and substrate. This combining of coupling elements simplifies the overall structure while maintaining the necessary electrical connections for half-bridge configuration, thus reducing device complexity while preserving functionality.
Solution Approach 2:
The patent applies different epitaxial layer structures to different regions - the first region has a first epitaxial layer optimized for the high-side switch while the second region has a second epitaxial layer optimized for the low-side switch. This local differentiation allows each switch to have optimal electrical characteristics while maintaining compact integration, thus managing the complexity of electrical coupling and separation requirements.
Data Source
AI summary
A semiconductor device and method are disclosed. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side. Contact areas of the first n-type channel FET and the second n-type channel FET are electrically separated from each other.