Monolithic Semiconductor Switches With Opposite-Side Contact Areas
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Solution Overview
Problem
There is a need to increase the integration level of semiconductor devices while maintaining appropriate device characteristics, particularly in motor drivers and DC-converters, where field effect transistors (FETs) are used in half-bridge configurations as semiconductor switches.
Innovation Solution
A semiconductor device is designed with a first and a second FET monolithically integrated in a half-bridge configuration on a single semiconductor die, where source/drain and gate connections are electrically coupled to contact areas on opposite sides of the die, allowing for a high-side and low-side switch configuration, utilizing various FET types such as n-type lateral and trench MOSFETs with specific doping and epitaxial layers for enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FETs are integrated in half-bridge configuration on a single semiconductor die, then integration level is increased, but device characteristics may deteriorate
Solution Approach 1:
The semiconductor die is divided into two opposite sides for contact area placement: first contact areas for source/drain connections and second contact areas for gate connections. This spatial segmentation allows independent optimization of source/drain and gate characteristics while maintaining monolithic integration, thus improving integration level without compromising device characteristics.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional spatial arrangement by placing contact areas on opposite sides of the semiconductor die. This dimensional change enables complex half-bridge configurations with multiple FETs while maintaining clear electrical separation and appropriate device characteristics.
2Productivity
If source/drain and gate connections are electrically coupled to contact areas on opposite sides of the die, then integration is improved, but manufacturing complexity increases
Solution Approach 1:
Multiple source/drain connections are merged into first contact areas on one side of the die, while multiple gate connections are merged into second contact areas on the opposite side. This merging approach simplifies the overall connection configuration despite the three-dimensional routing requirements, making the manufacturing process more manageable.
3Reliability
If FET components are electrically separated and coupled to opposite contact areas, then device performance is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent establishes predetermined locations for first and second contact areas on opposite sides of the semiconductor die during the design and fabrication planning stage. This preliminary positioning of contact areas provides clear manufacturing targets, reducing the actual precision requirements during the fabrication process while still achieving the desired electrical separation and performance enhancement.
Data Source
AI summary
One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides one semiconductor die with a first and a second FET. One of source/drain of the first FET and one of source/drain of the second FET are electrically coupled to at least one contact area at a first side of one semiconductor die, respectively. The other one of source/drain of the first FET, a gate of the first FET, the other one of source/drain of the second FET and the gate of the second FET are electrically coupled to contact areas at a second side of the one semiconductor die opposite to the first side, respectively. The contact areas of the other one of source/drain of the first FET, of the gate of the first FET, of the other one of source/drain of the second FET and of the gate of the second FET are electrically separated from each other, respectively.