Monolithic Sensor Fabrication via Native Oxide Removal
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Solution Overview
Problem
Current mid-IR imaging devices face challenges such as high costs, low yield, and reliability issues due to the hybrid approach of separate photodiode and readout integrated circuit chips, as well as thermal expansion mismatches that can lead to connection failures in cryogenic conditions.
Innovation Solution
A method for fabricating a monolithic sensor unit by removing the native oxide layer and using a wet etch process to achieve uniform gate recess depth and profile in field-effect transistors, allowing for integration of InSb-based photodiodes with GaAs-based transistors on a single chip, eliminating the need for separate chips and improving thermal stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a hybrid approach with separate photodiode and readout integrated circuit chips is used, then mid-IR imaging devices can be fabricated with current technology, but the manufacturing cost increases and yield decreases
Solution Approach 1:
The patent merges the photodiode and readout integrated circuit onto a single substrate, eliminating the need for separate chips and their interconnections. This monolithic integration directly reduces fabrication process complexity while improving connection reliability by removing the hybrid bonding interface that is prone to failure.
Solution Approach 2:
The patent segments the device into distinct functional layers (photodiode layer and readout circuit layer) that are fabricated separately but integrated monolithically on the same substrate. This allows independent optimization of each layer while maintaining simple overall fabrication and reliable integration.
2Manufacturing precision
If flip-chip bonding with indium bumps is used to connect separate chips, then large format and high performance imagers can be produced, but the fabrication cost and complexity increase due to additional steps
Solution Approach 1:
By combining the photodiode and readout circuit on a single substrate, the patent eliminates the flip-chip bonding process entirely. This removes the need for indium bump fabrication, chip flipping, and precise alignment steps, dramatically simplifying the manufacturing process while maintaining high precision through monolithic integration.
3Reliability
If separate photodiode and readout circuit chips are used, then mid-IR detection can be achieved, but the device reliability decreases under cryogenic cooling conditions
Solution Approach 1:
The patent merges both components on a single substrate made of the same material, eliminating the heterojunction between different materials. This removes the thermal expansion mismatch that causes stress and connection failure under cryogenic cooling, thereby improving thermal stability and reliability.
4Manufacturing precision
If a wet etch process is used to form gate recess, then uniform gate recess depth and profile can be achieved, but the fabrication process time increases
Solution Approach 1:
The patent applies a native oxide removal solution before the wet etch process to prepare the surface. This preliminary action ensures that the subsequent wet etch proceeds uniformly across the entire surface, achieving consistent gate recess depth and profile without requiring extended etching time or multiple etching steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of large, high-resolution sensor arrays with uniform response and reduced fabrication steps, enhancing the scalability and reliability of mid-IR imaging devices while reducing costs.
Implementation Method 1
performing a wet etch process on a portion of the first semiconductor device layer to form a gate recess in the first semiconductor device layer
Implementation Method 2
applying a native oxide removal solution to remove native oxide from the exposed surface of the first semiconductor device layer
Data Source
Figure 1
Figure 2A~2D
Figure 3A~3B
AI summary
A method of fabricating a field-effect transistor in which a native oxide layer is removed prior to etching a gate recess. The cleaning step ensures that the etch of the gate recess starts at the same time across an entire sample, such that a uniform gate recess depth and profile can be achieved across an array of field-effect transistors. This results in a highly uniform switch-off voltage for the field-effect transistors in the array.