Monolithic Bidirectional SiC JFET Switch With Lower On-Resistance
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Solution Overview
Problem
Conventional bidirectional switches using silicon carbide (SiC) JFETs for solid state circuit breakers (SSCBs) face challenges in reducing chip area and specific on-resistance, leading to increased cost and capacitance, while maintaining high voltage blocking capability.
Innovation Solution
A monolithically integrated bidirectional SiC JFET device is designed with two JFET devices connected in anti-series, each comprising multiple subcells, and a reduced surface charge (RESURF) region to minimize specific on-resistance and chip area, utilizing a silicon carbide substrate and alternating mesa stripes and trenches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bidirectional switches using SiC JFETs are used for SSCBs, then high voltage blocking capability is maintained, but chip area and specific on-resistance increase leading to higher cost and capacitance
Solution Approach 1:
The patent merges two JFET devices into a single monolithic bidirectional device by connecting them in anti-series on the same chip. This integration reduces the total chip area compared to using two separate JFET devices, while maintaining the ability to block high voltages in both directions through the anti-series configuration.
Solution Approach 2:
The patent transitions from a lateral JFET structure to a vertical JFET structure. This dimensional change allows for reduced specific on-resistance and optimized current flow paths, improving device performance while reducing the chip area required for high voltage blocking.
2Reliability
If conventional bidirectional switches using SiC JFETs are used for SSCBs, then high voltage blocking capability is maintained, but specific on-resistance increases leading to higher cost and capacitance
Solution Approach 1:
The patent transitions from a lateral JFET structure to a vertical JFET structure. This dimensional change allows for reduced specific on-resistance and optimized current flow paths, improving device performance while reducing the chip area required for high voltage blocking.
Solution Approach 2:
The patent optimizes key parameters including doping concentrations in the drift region and gate regions, as well as the geometry of the vertical structures, to achieve low specific on-resistance while maintaining high voltage blocking capability. These parameter changes are critical for reducing conduction losses and overall device cost.
3Reliability
If larger chip area is used to maintain voltage blocking capability, then reliability is improved, but cost and capacitance increase
Solution Approach 1:
The patent merges two JFET devices into a single monolithic bidirectional device by connecting them in anti-series on the same chip. This integration reduces the total chip area compared to using two separate JFET devices, while maintaining the ability to block high voltages in both directions through the anti-series configuration.
Solution Approach 2:
The patent transitions from a lateral JFET structure to a vertical JFET structure. This dimensional change allows for reduced specific on-resistance and optimized current flow paths, improving device performance while reducing the chip area required for high voltage blocking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces chip area and specific on-resistance, enabling faster switching and lower costs for high voltage applications, while maintaining effective voltage blocking capabilities.
Implementation Method 1
The active region acts as a main junction or region for blocking voltage in the reverse bias direction and providing current flow in the forward bias direction
Implementation Method 2
a reduced surface charge (RESURF) region to minimize specific on-resistance and chip area
Data Source
AI summary
A semiconductor device includes a substrate and a drift layer on the substrate, the drift layer having a first conductivity type. The device includes a first plurality of vertical junction field effect (JFET) subcells and a second plurality of vertical JFET subcells on the drift layer. The first plurality of vertical JFET subcells are connected in parallel to form a first JFET device, and the second plurality of vertical JFET subcells are connected in parallel to form a second JFET device. The second JFET device is connected in anti-series with the first JFET device through the drift layer. The device further includes a first gate electrode and a first current terminal in contact with the first plurality of vertical JFET subcells, and a second gate electrode and a second current terminal in contact with the second plurality of vertical JFET subcells.