Layer-by-Layer Fault Testing for Monolithic Stacked ICs
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Solution Overview
Problem
Conventional fault testing methods for monolithic stacked integrated circuits are inadequate as they require complete logic across multiple layers, leading to yield loss and inefficiencies, as they cannot effectively detect defects until all layers are built, making it challenging to isolate manufacturing issues in each layer during the fabrication process.
Innovation Solution
The implementation of a layer-by-layer fault testing approach, known as known-good-layer (KGL) testing, which involves inserting test circuits and generating test patterns for each layer during the fabrication of monolithic stacked ICs, allowing for defect detection and isolation as each layer is fabricated, using scan chains and multiplexers to facilitate testing across layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fault testing methods are used for monolithic stacked ICs, then complete logic across multiple layers is required for testing, but this leads to yield loss and inability to detect defects until all layers are built
Solution Approach 1:
The patent divides the monolithic stacked IC into individual layers, each with its own test circuits and scan chains. This segmentation allows testing to be performed on each layer independently as it is formed, rather than requiring complete logic across all layers. The test circuits are inserted at interconnect levels between layers, enabling layer-by-layer fault detection and eliminating yield loss from waiting for complete device fabrication.
2Ease of manufacture
If complete logic spans over multiple layers, then fault testing can be performed with KGD concept, but this prevents early defect detection and isolation per layer
Solution Approach 1:
The patent introduces test circuits and scan chains as intermediary elements at the interconnect levels between layers. These intermediaries provide access points for testing individual layers without requiring complete logic across all layers. The scan chains are configured to traverse through interconnect levels, enabling test patterns to be applied and responses to be captured for each layer independently, thus facilitating defect isolation per layer.
3Measurement precision
If testing is performed after all layers are built, then complete fault coverage can be achieved, but this increases manufacturing costs and reduces productivity
Solution Approach 1:
The patent implements preliminary testing actions at each layer formation stage by inserting test circuits and applying test patterns during the fabrication process. This preliminary action allows defects to be detected and defective layers to be removed early, preventing waste of subsequent processing steps. The scan chains are configured in advance to enable comprehensive fault coverage while maintaining manufacturing efficiency through early defect detection.
Data Source
AI summary
A method for testing a monolithic stacked integrated circuit (IC) is provided. The method includes receiving a layer of the IC. The layer has a first surface and a second surface, and the layer includes a substrate. The method further includes attaching probe pads to the first surface, and applying a first fault testing to the IC through the probe pads. The method further includes forming another layer of the IC over the second surface, and applying a second fault testing to the IC through the probe pads.