Monolithic Trench MOS Schottky Integration
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Solution Overview
Problem
Conventional power management devices using trench vertical double-diffused metal-oxide semiconductor (VDMOS) devices face issues such as parasitic inductance and high reverse leakage current due to the integration of trench MOS Schottky barrier (TMBS) devices as discrete components, which are costly and inefficient compared to monolithic integration.
Innovation Solution
The integration of trench MOS Schottky barrier devices into a standard integrated circuit process, such as a 1.5 μm bi-CMOS-DMOS (BCD) process, allows for monolithic integration, reducing parasitic inductance and reverse leakage current through the use of trench structures and conductive layers, and the incorporation of guard rings to enhance device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If trench MOS Schottky barrier devices are integrated as discrete components, then device functionality is achieved, but parasitic inductance increases and manufacturing cost increases
Solution Approach 1:
The patent merges the TMBS device with the control integrated circuit into a single monolithic structure, eliminating the need for separate discrete components and multi-chip connections. This integration removes parasitic inductance associated with external connections while maintaining full device functionality within the semiconductor substrate.
2Use of energy by moving object
If metal layer with lower barrier height is used, then forward voltage drop is reduced, but reverse leakage current increases
Solution Approach 1:
The patent applies different doping concentrations and metallurgical structures at different locations within the Schottky barrier region. By creating localized variations in the metal-semiconductor interface properties, the device achieves optimized forward voltage characteristics in the contact region while maintaining low leakage current through carefully engineered depletion regions and guard rings.
3Object-generated harmful factors
If metal layer with higher barrier height is used, then reverse leakage current is reduced, but forward voltage drop increases
Solution Approach 1:
The patent modifies key parameters including metal layer thickness, doping concentration profiles, and metallurgical bonding conditions to optimize the Schottky barrier properties. By precisely controlling these parameters during fabrication, the device achieves an optimal balance between forward voltage drop and reverse leakage current that cannot be obtained with conventional discrete structures.
4Reliability
If multi-chip technology is used to connect discrete device to control circuit, then device functionality is achieved, but parasitic inductance increases and manufacturing cost increases
Solution Approach 1:
The patent combines the TMBS device and control circuit fabrication into a single integrated manufacturing process. This monolithic integration eliminates multiple discrete fabrication steps, chip assembly operations, and inter-chip connections, thereby reducing manufacturing complexity and cost while improving device performance through eliminated parasitic elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the cost and improves the performance of power management devices by minimizing parasitic inductance and leakage current, enabling efficient and cost-effective integration of TMBS devices within integrated circuits.
Implementation Method 1
A TMBS device typically represents a synthesis of planar Schottky and trench technologies that produces a reduction in a surface electric field of the device (due to the 'super-junction' effect). This effect reduces the electric field at the Schottky interface, lowering the leakage current and increasing the breakdown voltage of the TMBS device. This may be achieved by extending the depletion region for a given voltage into a semiconductor substrate, such as by merging two opposing depletion regions.
Data Source
AI summary
Trenches are formed in a semiconductor substrate, where the trenches include an outer trench and multiple inner trenches within the outer trench. A metal-oxide semiconductor (MOS) device and a trench MOS Schottky barrier (TMBS) device are also formed in the semiconductor substrate using the trenches. The MOS device could include the outer trench, and the TMBS device could include the inner trenches. At least one of the inner trenches may contact the outer trench, and/or at least one of the inner trenches may be electrically isolated from the outer trench. The MOS device could represent a trench vertical double-diffused metal-oxide semiconductor (VDMOS) device, and the TMBS device may be monolithically integrated with the trench VDMOS device in the semiconductor substrate. A guard ring that covers portions of the inner trenches and that is open over other portions of the inner trenches could optionally be formed in the semiconductor substrate.