Monolithic Multi-Phase Voltage Regulator Layout
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Solution Overview
Problem
Multi-phase voltage regulators face inefficiencies and large size due to separate discrete components for gate driver circuits and switches, leading to high interconnection resistance and parasitic inductance, which increases cost and volume.
Innovation Solution
Integrating gate drivers closely with MOSFET transistors in a monolithic solution, where each phase comprises arrays of high and low side switching elements with gate drivers and MOSFET transistors connected in series, reducing interconnection resistance and parasitic capacitance, and manufacturing on a shared semiconductor substrate to form a compact integrated circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate driver circuits and switches are laid out as separate discrete components, then ease of manufacture is improved, but interconnection resistance and parasitic inductance increase leading to reduced efficiency
Solution Approach 1:
The patent merges the gate driver circuit and the power switch into a single integrated unit where the gate driver is directly connected to the gate of the power switch on the same semiconductor substrate. This integration eliminates separate discrete components and their interconnections, thereby reducing interconnection resistance and parasitic inductance while maintaining ease of manufacture through monolithic fabrication processes.
2Device complexity
If gate driver circuits and switches are laid out as separate discrete components, then device complexity is reduced, but volume increases due to larger current carrying requirements
Solution Approach 1:
The patent combines the gate driver circuit and power switch into a single integrated structure on the semiconductor substrate. This integration significantly reduces the overall volume by eliminating the need for separate discrete components, larger current carrying traces, and extensive interconnections, while the internal complexity is managed through systematic circuit design.
3Loss of energy
If Multi-Chip Modules are used to attach driver chip and switch chip on the same lead frame, then parasitic inductance is reduced, but current carrying ability is limited and size remains large
Solution Approach 1:
The patent integrates both the gate driver circuit and power switch transistors on the same semiconductor substrate using standard CMOS or BiCMOS fabrication processes. This monolithic integration provides superior current carrying ability compared to MCM approaches, as the power devices can be designed with optimized current paths and larger device geometries directly on the substrate, while achieving minimal parasitic inductance through direct on-chip connections.
4Reliability
If multiple inductors, switches, and capacitors are used in multi-phase systems, then multi-phase advantages are maintained, but cost increases
Solution Approach 1:
The patent integrates multiple phases of voltage regulation on a single semiconductor substrate, with each phase containing its own integrated gate driver and power switch. This multi-phase integration maintains the advantages of multi-phase operation (reduced ripple, improved efficiency, lower output capacitance requirements) while significantly reducing component count and overall system cost compared to discrete implementations.
Solution Approach 2:
The semiconductor substrate serves multiple functions simultaneously: it acts as the base for power switch implementation, gate driver integration, interconnection routing, and thermal management. This multi-functional integration consolidates what would otherwise require multiple separate components, thereby reducing cost while maintaining multi-phase performance advantages.
Data Source
AI summary
A multi-phase voltage regulator is disclosed where each phase is comprised of an array of high and low side transistors that are integrated onto a single substrate. Further, a system of mounting the voltage regulator onto a flip chip and lead frame is disclosed wherein the source and drain lines form an interdigital pattern.