In-Memory Computing Neural Network Mono-Pulse Input Signal
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Solution Overview
Problem
Existing in-memory computing architectures for neural networks face challenges in improving energy efficiency due to high energy consumption from analog-to-digital converters and input spikes.
Innovation Solution
The method involves generating a mono-pulse input signal based on discrete time coding, which is input into a memory array to generate a bit line current signal. This signal is then used to control a neuron circuit to output a mono-pulse output signal, which is configured as a mono-pulse input signal for the next layer in the next computing cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If mixed-signal input coding is used in in-memory computing architecture, then computing capability is improved, but energy consumption increases due to analog-to-digital converters
Solution Approach 1:
The patent extracts and removes the energy-intensive analog-to-digital converter from the in-memory computing architecture by adopting pure digital coding schemes (one-hot coding, binary coding, or ternary coding), thereby eliminating the harmful energy consumption while preserving computing capability
Solution Approach 2:
The patent changes the coding parameter representation from analog mixed-signal to discrete digital values (one-hot, binary, ternary), fundamentally altering how input data is encoded and processed in the memory array, which reduces energy consumption while maintaining computational functionality
2Loss of energy
If spike rate input coding is used to avoid analog-to-digital converters, then converter energy consumption is reduced, but total energy consumption increases due to large number of input spikes
Solution Approach 1:
The patent uses compact digital coding schemes (one-hot, binary, or ternary coding) that represent input values with fewer bits than spike rate coding, thereby performing the necessary computation with partial rather than excessive input signals, which reduces energy consumption
Solution Approach 2:
The patent replaces the physical implementation of multiple spikes with digital bit representations that copy the information content more efficiently, using binary or ternary digits to represent input values without requiring proportional physical spike events, thereby reducing energy consumption
3Adaptability or versatility
If Von Neumann architecture is used for neural network processing, then computational flexibility is maintained, but energy consumption increases due to data movement between arithmetic logic units and memory
Solution Approach 1:
The patent merges the storage and computing functions by implementing in-memory computing where neural network weight matrices are stored in memory arrays and computations are performed directly on the stored data, eliminating the need for repeated data movement between separate memory and processing units
Solution Approach 2:
The patent introduces digital coding schemes as an intermediary layer between input data and the in-memory computing array, enabling efficient digital-to-analog conversion only when needed for the actual computation, thereby reducing energy consumption compared to continuous analog conversion in traditional architectures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the number of input pulses and dynamic power consumption in the memory array and neural circuit, while maintaining high energy efficiency and compatibility with digital circuits.
Implementation Method 1
controlling the memory array to complete matrix-vector multiplication based on the input mono-pulse input signal to generate the bit line current signal
Data Source
AI summary
The present disclosure provides a method and an apparatus for operating an in-memory computing architecture applied to a neural network and a device, the method includes: generating a mono-pulse input signal based on discrete time coding; inputting the mono-pulse input signal into a memory array of the in-memory computing architecture to generate a bit line current signal corresponding to the memory array; and controlling a neuron circuit of the in-memory computing architecture to output a mono-pulse output signal based on discrete time coding according to the bit line current signal, wherein the mono-pulse output signal is configured as a mono-pulse input signal of a memory array of the next layer of neural network in the next in-memory computing cycle.