Split-Gate MONOS Memory Gate Length Control via Dual Etching
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Solution Overview
Problem
The manufacturing of split gate-type MONOS memory semiconductor devices faces challenges in achieving consistent memory characteristics due to variations in the gate length of memory gate electrodes, which are influenced by the shape of the control gate electrode, leading to issues with writing speed, erasing speed, and retention characteristics.
Innovation Solution
The method involves controlling the etching conditions to form a control gate electrode with a tailored shape, specifically using a first dry etching process with high anisotropy followed by a second dry etching process with lower anisotropy to achieve a desired tail shape, allowing for precise control of the gate length of the memory gate electrode, thereby ensuring consistent memory characteristics across different wafers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If a first etching process with high anisotropy is performed to form the control gate electrode, then the vertical profile of the gate electrode is improved, but the gate length becomes difficult to control precisely due to over-etching
Solution Approach 1:
The etching process is divided into two distinct stages: a first etching process with high anisotropy to establish the vertical profile, and a second etching process with low anisotropy to precisely control the gate length. This segmentation allows each process to optimize for its specific function, resolving the contradiction between vertical profile and gate length control.
Solution Approach 2:
The first etching process with high anisotropy is performed first to pre-form the vertical profile of the control gate electrode. This preliminary action creates a foundation that the second etching process can then refine, ensuring both vertical profile quality and precise gate length control.
2Shape
If the etching amount of the first etching process is increased to achieve the desired vertical profile, then the vertical shape is improved, but the gate length varies due to shape variation of the control gate electrode
Solution Approach 1:
The etching process is segmented into two independent controllable stages, allowing the first process to focus on vertical shape formation while the second process precisely controls the gate length. This segmentation prevents the coupling of shape and length variations, improving reliability.
Solution Approach 2:
The invention changes the etching parameters (anisotropy level, etching amount) between the two processes. The first process uses high anisotropy for vertical profiling, while the second uses low anisotropy with controlled etching amount for precise gate length control, thereby decoupling shape and length control.
3Productivity
If a batch system is used for film forming to reduce manufacturing cost, then productivity is improved, but it becomes difficult to form memory gate electrodes with different gate lengths on different wafers
Solution Approach 1:
The control gate electrode shape, including the tail length, is pre-formed through the two-stage etching process before the memory gate electrode formation. This preliminary action on the control gate allows subsequent batch processing of memory gates with different lengths without requiring batch formation of different control gate shapes.
Solution Approach 2:
The invention applies local quality control by forming different tail lengths of the control gate electrode in specific local regions through the two-stage etching process. This allows batch processing while maintaining the ability to create locally differentiated gate lengths for different memory applications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the defective rate of semiconductor devices, improves reliability, and enables the production of memory cells with specific performance characteristics, such as varying writing and erasing speeds and retention properties, while maintaining constant resistance and reducing manufacturing costs.
Implementation Method 1
a first etching process having a high anisotropy
Implementation Method 2
a second etching process having a low anisotropy
Data Source
AI summary
In a split-gate-type MONOS memory, increase in a defective rate due to variation in a gate length of a memory gate electrode is prevented, and reliability of a semiconductor device is improved. A first dry etching having a high anisotropic property but a low selection ratio relative to silicon oxide is performed to a silicon film, and then, a second dry etching having a low anisotropic property but a high selection ratio relative to silicon oxide is performed thereto, so that a control gate electrode composed of the silicon film is formed, and then, a sidewall-shaped memory gate electrode is formed on a side surface of the control gate electrode. In this case, respective etching amounts of the first dry etching and the second dry etching are controlled by determining a length of etching time in accordance with desired characteristics of a manufactured memory and a film thickness of the silicon film in the first dry etching, based on an etching time setting table, so that a gate length of the memory gate electrode is controlled.