Split-Gate MONOS Memory Halo Region Manufacturing
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Solution Overview
Problem
In the miniaturization of split-gate memory cells, there is a trade-off between improving short channel characteristics and reducing miswriting, as increasing the impurity concentration to enhance threshold voltage can lead to increased miswriting due to junction leakage currents.
Innovation Solution
A method of manufacturing semiconductor devices with a halo region on the drain side of split-gate MONOS memory cells, where the source region has a larger depth than the drain region, to suppress the spread of the depletion layer and maintain adequate threshold voltage without excessive impurity concentration differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If impurity concentration is increased to enhance threshold voltage, then short channel characteristics are improved, but miswriting increases due to junction leakage currents
Solution Approach 1:
The patent applies different impurity concentrations to different regions: the source region has a first impurity concentration while the drain region has a second impurity concentration that is lower than the first. This local differentiation allows the source region to provide adequate threshold voltage while the drain region maintains lower leakage current, resolving the contradiction between threshold voltage stability and miswriting prevention
Solution Approach 2:
The patent creates an asymmetric structure where the source and drain regions have different impurity concentrations. The source region is designed with higher impurity concentration to ensure proper threshold voltage, while the drain region uses lower impurity concentration to minimize junction leakage currents that cause miswriting. This asymmetric design breaks the symmetry between source and drain to optimize their respective functions
2Productivity
If memory cell size is reduced for miniaturization, then device density increases, but short channel effects worsen
Solution Approach 1:
By assigning different impurity concentrations to source and drain regions, the patent locally optimizes each region's properties. The source region's higher impurity concentration compensates for short channel effects in miniaturized devices, while maintaining overall device density through the asymmetric design
Data Source
AI summary
A method of manufacturing a semiconductor device having a memory cell for a split-gate MONOS memory with a halo region, which prevents miswriting in the memory cell and worsening of short channel characteristics. In the method, a first diffusion layer of a drain region and a second diffusion layer of a source region in the memory cell for the MONOS memory are formed in different ion implantation steps. The steps are carried out so that the first diffusion layer has a smaller formation depth than the second diffusion layer. After the formation of the layers, the impurities inside the first and second diffusion layers are diffused by heat treatment to form a first diffusion region and a second diffusion region.