MONOS Memory Cell Charge Trapping Layer Localization

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Solution Overview

Problem

In MONOS memory cells, hot electron and hot hole injection methods lead to charge injection into unintended regions, causing gate-induced drain leakage, error writing, and increased capacitance, which hampers reliability and speed, especially in miniaturized designs with multi-valued structures.

Innovation Solution

The charge trapping layer is formed only in the element formation region, and the element isolation region is designed without the charge trapping layer, reducing capacitance and preventing charge diffusion, thereby enhancing reliability and operation speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the charge trapping layer is formed in the element isolation region, then the memory cell area is reduced, but charge diffusion occurs leading to gate-induced drain leakage and error writing

Engineering Contradiction:

Improvememory cell areaVSAvoiderror resistance

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The charge trapping layer is selectively formed only in the element formation region where memory cells are located, while intentionally excluding the element isolation regions. This local differentiation prevents charge diffusion into isolation regions, eliminating gate-induced drain leakage and error writing, while still providing sufficient charge trapping capability within the element formation region to maintain memory functionality.

Inventive Principle:

Principle #3Local quality

2Productivity

If the charge trapping layer is formed in the element isolation region, then device integration is improved, but capacitance increases reducing operation speed

Engineering Contradiction:

Improvedevice integrationVSAvoidoperation speed

Core Design Contradiction:

ProductivityVSSpeed

Solution Approach 1:

The charge trapping layer is localized exclusively to the element formation region, creating a spatially differentiated structure where charge trapping functionality exists only where needed for memory operation. This eliminates unnecessary capacitance in the element isolation regions, thereby improving operation speed while maintaining adequate integration through efficient use of the element formation region space.

Inventive Principle:

Principle #3Local quality

3Ease of operation

If hot electron and hot hole injection methods are used, then writing and erasing operations are achieved, but charges are injected into unintended regions causing gate-induced drain leakage

Engineering Contradiction:

Improvewriting and erasing capabilityVSAvoidgate-induced drain leakage

Core Design Contradiction:

Ease of operationVSReliability

Solution Approach 1:

The invention accepts that hot electron and hot hole injection will occur during normal writing and erasing operations, but converts the potential harm by strategically positioning the charge trapping layer only in the element formation region. This ensures that even if charges are injected into unintended regions, they cannot diffuse into element isolation regions to cause gate-induced drain leakage, thereby eliminating the harmful effect while preserving the beneficial writing and erasing operations.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the reliability and operation speed of MONOS memory cells by preventing unwanted charge injection and diffusion, reducing capacitance, and enhancing error resistance, especially in miniaturized and multi-valued structures.

Implementation Method 1

information is written or erased by injecting hot electrons or hot holes into the charge trapping layer

Methodology Applied

Scientific EffectHot electron injection:

Implementation Method 2

information is written or erased by injecting hot electrons or hot holes into the charge trapping layer

Methodology Applied

Scientific EffectHot hole injection:

Implementation Method 3

element isolation insulating films are formed in a semiconductor substrate, by which the interference of current between adjacent memory cells is prevented and elements are isolated from each other

Methodology Applied

Scientific EffectElectrical isolation:

Data Source

PatentUS7687845B2Nonvolatile semiconductor storage device having an element formation region and a plurality of element isolation regions and manufacturing method of the same

Publication Date: 2010.03.30 RENESAS ELECTRONICS CORP

AI summary

A charge trapping layer in an element isolation region and that in an isolation region between a memory transistor and a selection transistor are removed so that the charges are not injected or trapped in the regions. Also, in an element isolation region, gate electrodes of each memory transistor are united at a position higher than a gate electrode of the selection transistor from a surface of a silicon substrate in an element isolation region, thereby reducing the capacitance between the memory transistor and the selection transistor.