Fin-Type MONOS Memory Gate Impurity Gradient for Uniform Electron Injection

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Solution Overview

Problem

In FINFET-based MONOS memory devices, electric field concentration at the upper surface of the fin leads to uneven write characteristics, reducing write lifetime and deteriorating memory performance due to differences in electron injection distribution between the upper and side surfaces.

Innovation Solution

A semiconductor device with a MONOS memory structure where the impurity concentration of the memory gate electrode above the fin is lower than that below the upper surface, and phosphorus is introduced into the upper surface adjacent to the source region, optimizing the electron injection distribution and preventing unbalanced injection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If a FINFET structure is used to downsize the memory device, then the device can be downsized and operated with reduced leakage current, but electric field concentration occurs at the upper surface of the fin causing uneven write characteristics and reduced write lifetime

Engineering Contradiction:
Improvedevice sizeVSAvoidwrite lifetime
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The patent applies local quality by creating different impurity concentration regions within the memory gate electrode. Specifically, the first region (above the fin upper surface) has a different impurity concentration than the second region (below the fin upper surface), allowing localized control of electrical characteristics to balance electron injection between the upper and side surfaces of the fin, thereby resolving the uneven write characteristics caused by electric field concentration

Inventive Principle:
Principle #3Local quality

2Device complexity

If the memory gate electrode has uniform impurity concentration, then the device structure is simple, but electron injection becomes unbalanced between the upper surface and side surface of the fin, deteriorating write characteristics

Engineering Contradiction:
Improvegate electrode structureVSAvoidwrite characteristics
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent implements local quality by dividing the memory gate electrode into regions with different impurity concentrations. The first region positioned above the fin upper surface has a specific impurity concentration, while the second region below the fin upper surface has a different concentration. This localized differentiation optimizes electron injection distribution to achieve balanced write characteristics across the fin structure

Inventive Principle:
Principle #3Local quality

3Reliability

If phosphorus is introduced into the upper surface of the fin, then electron injection distribution is optimized and write characteristics are improved, but the manufacturing process becomes more complex

Engineering Contradiction:
Improvewrite characteristicsVSAvoidmanufacturing process
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies parameter changes by controlling the impurity concentration distribution in the memory gate electrode. By adjusting the impurity concentration in different regions (first region above the fin and second region below the fin), the patent optimizes electron injection characteristics and write performance while managing manufacturing complexity through controlled parameter variation

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration improves the reliability of the semiconductor device by ensuring uniform electron injection and extending the write lifetime, preventing deterioration in write characteristics and endurance.

Implementation Method 1

immediately below a memory gate electrode configuring a memory cell, phosphorus is introduced into the upper surface of a fin adjacent to a source region configuring the memory cell

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS10217759B2Semiconductor device
Publication Date: 2019.02.26 RENESAS ELECTRONICS CORP
  • US10217759B2 patent drawing
  • US10217759B2 patent drawing
  • US10217759B2 patent drawing

AI summary

To provide a semiconductor device having improved reliability by preventing, in a split-gate MONOS memory comprised of a fin type transistor, unbalanced injection distribution of electrons into a charge accumulation film due to the shape of the fin. A memory gate electrode configuring a memory cell is formed over a fin. The impurity concentration of a portion of this memory gate electrode contiguous to an ONO film that covers the upper surface of the fin is made lower than that of a portion of the memory gate electrode contiguous to an ONO film that covers the side surface of the fin.