Split Gate MONOS Memory Cell Selective Erase via Fin Structure
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Solution Overview
Problem
Existing semiconductor devices with split gate type MONOS memory face challenges in selectively erasing memory cells due to the need for simultaneous erase operations across multiple cells in a row, leading to increased device area requirements and reduced storage capacity.
Innovation Solution
The semiconductor device employs a fin-type transistor structure with a split gate type MONOS memory, utilizing the FN method for erase operations, where unselected memory cells have an open drain electrode and a positive voltage applied to the memory gate electrode, creating an induced voltage region that prevents unwanted erasure, allowing for individual cell selection and reduced area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If bit-by-bit erase operation is performed in split gate type MONOS memory without well potential control, then device area is reduced, but individual memory cell selection during erase operation becomes impossible
Solution Approach 1:
The gate electrode is divided into two separate gates (first gate electrode and second gate electrode) that can be independently controlled. This segmentation allows selective application of voltages to different gate regions, enabling individual memory cell selection during erase operations while maintaining the compact split gate structure without requiring well potential control for each cell.
Solution Approach 2:
Different voltage conditions are applied to different regions of the gate electrodes to achieve local control over the erase operation. By applying specific voltage combinations to the first and second gate electrodes, the erase operation can be localized to specific memory cells or rows, providing selective erase capability without requiring individual well control for each cell.
2Area of stationary object
If simultaneous erase operation is performed on all memory cells in a row using parallel source line and memory gate line, then individual cell selection is lost, but device area can be minimized
Solution Approach 1:
The erase operation capability is made dynamic through independent control of the first and second gate electrodes. This allows the system to switch between row-wide erase operations and selective individual cell erase operations as needed, providing operational flexibility while maintaining the area-efficient parallel line structure.
Solution Approach 2:
Different voltage parameters are applied to the first and second gate electrodes to control the erase operation. By varying the voltage combinations and timing, the system can achieve both simultaneous row erase and selective individual cell erase, providing operational flexibility without changing the basic parallel line architecture.
3Ease of operation
If EEPROM structure with controlled well potential for each memory cell is used, then individual cell selection is achieved, but device area increases due to isolation requirements
Solution Approach 1:
The control functions previously requiring separate well structures for each cell are merged into the gate electrode system. By combining the selection and erase control functions into the independently controllable first and second gate electrodes, the patent eliminates the need for extensive well isolation structures, reducing device area while maintaining individual cell selection capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables selective erasure of memory cells, increasing storage capacity and scaling while minimizing the element area required for each bit of data, thereby improving the performance of the semiconductor device.
Implementation Method 1
a memory gate electrode is applied with a positive voltage, whereby an induced voltage region is generated in a channel region
Data Source
AI summary
A memory cell of a split gate type MONOS memory is formed over a plate-shaped fin being a part of a semiconductor substrate. In a data erase operation, in a selected memory cell on which erasing is performed, a drain region is applied with 0 V, a memory gate electrode is applied with a positive voltage, and accordingly, erasing is performed by the FN mechanism. Also, in the data erase operation, in an unselected memory cell on which the erasing is not performed, connected to the same memory gate line as the above-described selected memory cell, the drain region is in an open state, and the memory gate electrode is applied with the positive voltage, whereby an induced voltage region is generated in a channel region. Thus, a potential difference between the channel region and the memory gate electrode is small, and accordingly, the erasing is not performed.