Nitrogen Gradient MONOS Gate Insulator for Fast Erasing

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Solution Overview

Problem

Conventional MONOS type semiconductor memory devices face issues with long erasing time, significant variation in threshold voltage after erasing, and carrier movement leading to reliability concerns and errors.

Innovation Solution

A semiconductor memory device structure incorporating a nitrogen-containing silicon dioxide film with varying nitrogen composition, enclosed by insulation films with higher band gaps, concentrates electrical charges near the gate electrode for efficient erasing and reduced threshold voltage variation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If a conventional MONOS type semiconductor memory device uses a uniform nitrogen-containing silicon dioxide film, then the device can store information, but the erasing time becomes excessively long

Engineering Contradiction:
Improveerasing timeVSAvoiderasing speed
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The patent applies local quality by creating a nitrogen concentration gradient within the silicon dioxide film, where the nitrogen concentration varies from the semiconductor substrate interface toward the gate electrode interface. This non-uniform distribution optimizes different regions for different functions: the region near the substrate efficiently captures and neutralizes electrons during erasing, while the region near the gate maintains stable threshold voltage, thereby resolving the contradiction between erasing speed and operational reliability.

Inventive Principle:
Principle #3Local quality

2Reliability

If electrical charges are dispersed throughout the insulation film, then information can be stored, but threshold voltage varies significantly after erasing

Engineering Contradiction:
Improvethreshold voltage stabilityVSAvoidthreshold voltage control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent utilizes local quality by designing a nitrogen concentration gradient that concentrates nitrogen atoms in specific regions of the silicon dioxide film. This creates localized zones with different electrical properties: the high-nitrogen region near the substrate efficiently neutralizes electrons, while the low-nitrogen region near the gate maintains stable threshold voltage, thereby achieving both reliable charge storage and precise threshold voltage control.

Inventive Principle:
Principle #3Local quality

3Reliability

If a silicon nitride film is used as the insulation film with trap levels, then information storage is enabled, but carrier movement causes reliability issues and errors

Engineering Contradiction:
Improvedata retention reliabilityVSAvoidcarrier movement
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies parameter changes by transitioning from a uniform nitrogen-containing silicon dioxide film to one with a controlled nitrogen concentration gradient. This parameter variation optimizes the electrical properties of different regions within the film, creating zones that selectively attract and neutralize carriers while preventing unwanted carrier movement, thereby improving data retention reliability without generating harmful side effects.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This structure enables faster erasing, reduces threshold voltage variation, and improves data retention by intensively accumulating and neutralizing electrical charges, enhancing the reliability and performance of the semiconductor memory device.

Implementation Method 1

Information is stored by capturing an electrical charge at the trap level that exists in this insulation film

Methodology Applied
Scientific EffectElectron trapping:

Implementation Method 2

A writing operation using channel hot electrons (Channel Hot Electron; CHE) of the MONOS type memory cell

Methodology Applied
Scientific EffectField emission:

Implementation Method 3

an erasing operation is carried out by implanting hot holes generated in the vicinity of the first impurity diffused layer 52 or the second impurity diffused layer 53 due to interband tunneling to the silicon nitride film 55 to neutralize the accumulated electrons

Methodology Applied
Scientific EffectInterband tunneling:

Data Source

PatentUS7821823B2Semiconductor memory device, method of driving the same and method of manufacturing the same
Publication Date: 2010.10.26 RENESAS ELECTRONICS CORP
  • US7821823B2 patent drawing
  • US7821823B2 patent drawing
  • US7821823B2 patent drawing

AI summary

Disclosed is a semiconductor storage device comprising a semiconductor substrate, a first and a second impurity diffusion layer formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a first gate electrode formed on the semiconductor substrate via the gate insulating film. The gate insulating film has a nitrogen-containing silicon oxide film inside, and a silicon oxide film is so arranged on both sides of the nitrogen-containing silicon oxide film as to sandwich the nitrogen-containing silicon oxide film. In addition, the nitrogen composition in the nitrogen-containing silicon oxide film is increased from the semiconductor substrate side to the first gate electrode side.