Monotonic Counter Layout for Atomic Low-Power Increments
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Solution Overview
Problem
Existing monotonic counter implementations are inefficient in incrementing operations, leading to high power consumption and reduced endurance due to the need for multiple writing and erasing operations, and lack atomicity in handling counter values.
Innovation Solution
A monotonic counter design that alternates between writing and erasing phases in each increment operation, where a single memory cell's value is incremented by doubling the step size and written to the next cell, and consecutive cells' lower-ranked values are erased, minimizing the number of operations and ensuring atomicity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional monotonic counter increment operations are implemented, then the counter value is updated, but multiple writing and erasing operations are required leading to high power consumption and reduced endurance
Solution Approach 1:
The counter is divided into N memory cells arranged in a circular buffer structure, where each cell stores a portion of the counter state. This segmentation allows the increment operation to be performed by updating only one or two cells at a time rather than rewriting the entire counter state, thereby reducing the number of write operations and associated power consumption.
Solution Approach 2:
The patent implements periodic alternation between writing phase and erasing phase in each increment operation. The control circuitry determines whether to perform a write or erase operation based on the current phase, allowing optimized execution paths that reduce overall power consumption compared to always performing full write operations.
2Duration of action of stationary object
If traditional monotonic counter increment operations are implemented, then the counter value is updated, but multiple writing and erasing operations are required leading to reduced endurance
Solution Approach 1:
By segmenting the counter into N memory cells, the patent reduces wear on individual cells since not all cells are written or erased on every increment operation. Only the active cell(s) undergo modification, extending the overall endurance of the counter structure while maintaining efficient update speed.
Solution Approach 2:
The patent recovers and reuses memory cell states through the circular buffer approach. When a cell is erased in one phase, it becomes available for writing in a subsequent phase, maximizing the utilization of each cell's write/erase cycles and improving both endurance and operational efficiency.
3Reliability
If traditional monotonic counter increment operations are implemented, then the counter value is updated, but atomicity is not ensured
Solution Approach 1:
The periodic alternation between writing and erasing phases provides a structured approach to ensuring atomicity. By completing either a full write or full erase operation atomically and alternating phases, the system guarantees that the counter state transitions are consistent and atomic, while the phase management adds controlled complexity to the control circuitry.
4Loss of energy
If the number of memory operations is reduced, then power consumption is lowered, but the counter must maintain monotonicity and atomicity
Solution Approach 1:
Segmenting the counter into N cells enables reduced operations while maintaining reliability. The segmentation allows the system to update only necessary cells and use the circular buffer structure to ensure that monotonicity is preserved even with fewer operations, as the structured state transitions guarantee atomic and monotonic updates.
Data Source
AI summary
The present disclosure relates to a monotonic counter whose value is represented by a number N of binary words of N memory cells of a non-volatile memory, and being able to implement a step increment operation wherein if only one first memory cell represents a first value different from zero, then a second value equal to the said first value incremented by two times the said step is written into a second memory cell of rank directly higher than the rank of the first memory cell; and if a third and a fourth memory cell of consecutive ranks represent, respectively, a third value and a fourth value different from zero, then the third value of the third memory cell of lower rank is erased.