Monotonic Counter Buffering to Preserve Flash Write Life
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Solution Overview
Problem
Flash memory's finite number of program-erase cycles limits the ability to maintain a monotonic counter's value, especially when incremented or decremented at a high rate, potentially leading to security compromises due to replay attacks.
Innovation Solution
Maintain the monotonic counter's value in volatile memory (SRAM or DRAM) and save it at defined intervals to non-volatile memory, using a constant step size to manage write cycles and ensure monotonicity across power cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the monotonic counter value is stored in flash memory to ensure persistence across power cycles, then the counter maintains its value through power-on and power-off cycles, but the finite number of program-erase cycles in flash memory is exhausted prematurely due to high-rate increment/decrement operations
Solution Approach 1:
The patent segments the storage function by using volatile memory (SRAM/DRAM) for frequent counter updates and non-volatile memory (Flash) only for periodic persistence. This segmentation allows the counter to be incremented/decremented at high rates in volatile memory without consuming flash program-erase cycles, while still maintaining persistence by periodically saving to Flash memory.
Solution Approach 2:
The patent introduces volatile memory as an intermediary between the counter operations and the flash memory. The volatile memory acts as a buffer that absorbs the high-frequency write operations, while only periodic or exceptional updates are propagated to the flash memory, thereby protecting the flash from premature wear.
2Reliability
If the monotonic counter is incremented or decremented at a high rate to meet security requirements, then the counter provides adequate security against replay attacks, but the number of write cycles to non-volatile memory exceeds the finite program-erase cycle limit
Solution Approach 1:
The patent divides the write operations into two categories: frequent incremental updates in volatile memory that do not consume flash cycles, and periodic persistence operations to flash memory. This segmentation enables high-rate counter operations to maintain security while preserving flash write cycle capacity for the device's expected lifetime.
Solution Approach 2:
The patent changes the storage medium parameter from exclusively non-volatile to a hybrid volatile-non-volatile approach. By utilizing volatile memory's high write speed and unlimited write cycles for frequent updates, the system maintains security requirements while avoiding the write cycle limitations of flash memory.
3Reliability
If the counter value is saved to non-volatile memory at every update to ensure data integrity, then the counter maintains accuracy, but the device寿命 is reduced due to excessive program-erase cycles
Solution Approach 1:
The patent implements preliminary action by maintaining the counter value in volatile memory where it can be updated without risk of data loss during normal operation. The system is designed to handle power loss scenarios by using the volatile memory's speed for immediate updates and relying on periodic or exception-based saves to non-volatile memory, rather than saving at every update.
Solution Approach 2:
The patent employs periodic action by saving the counter value to non-volatile memory at predetermined intervals or under specific conditions (such as before power-down or at scheduled checkpoints) rather than at every counter update. This periodic persistence maintains data integrity while dramatically reducing the frequency of flash program-erase cycles.
Data Source
AI summary
The present application relates to a system hosting a monotonic counter and a method of operating the system. The system comprises a non-volatile memory (110) for holding a save counter value and a volatile memory (120) for maintaining a current counter value. The system (100) is configured during a startup phase to retrieve the saved counter value of the monotonic counter from the non-volatile memory (110); to detect whether a previous shutdown of the system (100) was an uncontrolled shutdown; and to adjust the retrieved counter value in accordance with a step size (130) provided at the system (100) in case an previous uncontrolled shutdown is detected.