Monotonic Counter with Persistent Power Supply for Anti-Replay

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Solution Overview

Problem

Existing cryptographic systems on chip face challenges with data loss and aging due to high erasing and writing cycles in non-volatile memory-based monotonic counters, which are prone to power loss and slow incrementation, making them vulnerable to replay attacks and data integrity issues.

Innovation Solution

A system on chip architecture incorporating a monotonic counter with a volatile counter register fed by a persistent power supply, including a bus interface and command interpreter, which ensures data integrity and accelerates counter increments, using a power-loss register to detect and reset the counter in case of power loss, and a milestone bit registration mechanism for monotonicity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a non-volatile memory-based monotonic counter is used, then data persistence is achieved, but data loss and aging occur due to high erasing and writing cycles

Engineering Contradiction:

Improvedata persistenceVSAvoiddata loss and aging

Core Design Contradiction:

ReliabilityVSLoss of substance

Solution Approach 1:

The patent creates a copy of the counter value in volatile memory (RAM) that is continuously updated. Instead of directly writing to non-volatile memory for each increment, the system maintains a volatile copy that is periodically flushed to non-volatile memory, reducing wear while maintaining persistence.

Inventive Principle:

Principle #26Copying

Solution Approach 2:

The patent changes the state of the counter register from non-volatile to volatile memory, fundamentally altering how the counter operates. This allows the counter to be stored in RAM and only periodically committed to non-volatile memory, changing the parameters of data storage and access.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If a non-volatile memory-based monotonic counter is used, then data persistence is achieved, but incrementation speed is slow

Engineering Contradiction:

Improvedata persistenceVSAvoidcounter incrementation speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The patent maintains a volatile copy of the counter in RAM that can be incremented at full speed without the constraints of non-volatile memory. This volatile copy serves as a working buffer that is periodically flushed to non-volatile memory, allowing fast incrementation while maintaining persistence.

Inventive Principle:

Principle #26Copying

Solution Approach 2:

The patent segments the counter operation into two parts: a fast volatile memory counter for active incrementation and a persistent non-volatile memory counter for data retention. This segmentation allows each component to optimize for its specific function.

Inventive Principle:

Principle #1Segmentation

3Speed

If a volatile counter register with persistent power supply is used, then counter incrementation speed is accelerated, but power loss risk increases

Engineering Contradiction:

Improvecounter incrementation speedVSAvoidpower loss risk

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent introduces a persistent power supply (such as a battery or capacitor) as an intermediary between the volatile counter register and the main power supply. This intermediary maintains the counter value during brief power interruptions, acting as a buffer that protects against complete power loss while allowing the volatile register to operate at full speed.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent provides beforehand cushioning by implementing a persistent power supply that can maintain the counter register during anticipated power fluctuations. This protective measure is in place before actual power loss occurs, cushioning against the risk of data loss while enabling high-speed operation.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

4Reliability

If a monotonic counter is used for anti-replay mechanism, then replay attacks are prevented, but data integrity issues arise due to power loss and aging

Engineering Contradiction:

Improveanti-replay capabilityVSAvoiddata integrity

Core Design Contradiction:

ReliabilityVSLoss of information

Solution Approach 1:

The patent maintains a volatile copy of the monotonically increasing counter value that is continuously updated during operation. This volatile copy is periodically flushed to non-volatile memory, ensuring that the counter value used for anti-replay protection is both current and persistent, preventing replay attacks while maintaining data integrity.

Inventive Principle:

Principle #26Copying

Solution Approach 2:

The persistent power supply acts as an intermediary that protects the counter value during power loss events. By maintaining the counter register during brief interruptions, the persistent power supply ensures that the monotonically increasing sequence is preserved, maintaining data integrity and preventing replay attacks.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12045339B2System on chip for cryptography applications including a monotonic counter and method of operation

Publication Date: 2024.07.23 STMICROELECTRONICS SRL

AI summary

In an embodiment a system on chip includes a persistent power supply and anti-replay mechanism comprising a monotonic counter including a volatile counter register powered by the persistent power supply.