Monotonic Memory Counters for Power-Loss-Tolerant NAND
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Solution Overview
Problem
Memory systems, particularly non-volatile storage memories like NAND flash, are susceptible to data degradation and bit error rates, which can lead to issues such as replay attacks due to the need for frequent writing and lack of effective error correction codes, and power losses can result in lost counts.
Innovation Solution
Implementing a monotonic counter system with a volatile counter and a non-volatile memory array, where information is written only after a certain number of increments, using redundant bits to compensate for high bit error rates and ensuring a monotonically increasing count by initializing the counter upon power-up, and utilizing block swapping to maintain storage capacity and guard against power losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If information is written to the memory array each time the counter is incremented, then the count is continuously updated, but the memory array degrades faster due to excessive write operations
Solution Approach 1:
The system performs write operations only when necessary (every N increments) rather than continuously, reducing wear on the memory array while still maintaining count continuity through periodic updates and non-volatile storage
2Reliability
If the counter is initialized to a high value upon power-up, then power-loss tolerance is improved, but the counting range is reduced
Solution Approach 1:
The system uses multiple memory blocks (block 1 and block 2) to extend the counting range beyond what a single block can accommodate, while still initializing from a high value within each block to maintain power-loss tolerance
3Reliability
If redundant bits are added to compensate for bit error rates, then error correction capability is improved, but the storage capacity is reduced
Solution Approach 1:
The system changes the parameter of bit redundancy by using multiple copies of the same count value across different memory locations, allowing error correction through comparison rather than traditional redundancy encoding
Data Source
AI summary
An apparatus, such as a memory (e.g., a NAND memory), can have a controller, a volatile counter coupled to the controller, and a non-volatile memory array coupled to the controller. The controller can be configured to write information, other than a count of the counter, in the array each time the count of the counter has been incremented by a particular number of increments. Counts can be monotonic, non-volatile, and power-loss tolerant.