Monte Carlo Simulation Yield Estimation via Scaled-Sigma Sampling
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Solution Overview
Problem
Current methods for performing accurate statistical analysis of rare circuit failure events in integrated circuit (IC) design require lengthy calculations with large sample sets, leading to computational bottlenecks and increased turnaround time.
Innovation Solution
A computer-implemented method that uses a limited number of Monte Carlo simulations, employing scaled-sigma sampling and kernel density estimation to visualize and estimate the yield and failure rate of IC designs, allowing for reduced computational costs and faster design turnaround.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If large sample sets are used for Monte Carlo simulations to improve statistical analysis accuracy, then measurement precision is improved, but productivity deteriorates due to lengthy calculations and increased turnaround time
Solution Approach 1:
The patent transforms the simulation approach by changing parameters from uniform sampling across the entire parameter space to scaled-sigma sampling that concentrates samples in critical regions. By adjusting the sigma scaling factor and focusing on yield-critical regions, the method achieves accurate statistical analysis with fewer samples, resolving the contradiction between measurement precision and productivity
Solution Approach 2:
The patent segments the parameter space into critical and non-critical regions based on yield sensitivity. By identifying and separately analyzing yield-critical regions where failures are most likely to occur, the method concentrates computational resources where they provide maximum statistical value, achieving accurate failure rate estimation without requiring large overall sample sets
2Measurement precision
If large sample sets are used for Monte Carlo simulations to obtain accurate statistical samples, then measurement precision is improved, but loss of time increases due to computational bottlenecks
Solution Approach 1:
The patent performs preliminary identification of yield-critical regions and failure modes before executing the full Monte Carlo simulation. By pre-characterizing the parameter space to locate regions that contribute most to yield loss, the method prepares a targeted sampling strategy that eliminates wasted computational time in non-critical regions while maintaining statistical accuracy in critical areas
Data Source
AI summary
A method for visualizing a performance distribution of an integrated circuit (IC) design is provided. The method includes determining a yield limit based on a group of Monte Carlo simulations of the IC design, and a functional yield, and selecting an initial yield based on an initial specification value from the group of Monte Carlo simulations. The method also includes selecting additional yield values based on additional specification values and on the group of Monte Carlo simulations of the IC design, wherein the low yield values are estimated using Kernel Density Estimation, and the high yield values are estimated using repeated binary search. The cumulative distribution function and probability density function for a performance of the IC design are estimated based on the additional yield values and the additional specification values. Also, the method includes obtaining a quantile representation for the performance of the IC design from the cumulative distribution function.