Montgomery Multiplication Arithmetic Device Using Redundant Binary
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Solution Overview
Problem
Existing Montgomery multiplication methods require a large number of clock cycles and are inefficient when changing the number of processing bits, particularly in modular exponentiation operations, due to their sequential processing nature and high computational overhead.
Innovation Solution
An arithmetic device that calculates Montgomery multiplication results by converting integers to redundant binary representation and using shift amounts to optimize the number of operations, allowing for flexible bit processing and reducing the number of clock cycles required, similar to the ZDN method's efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional Montgomery multiplication methods are used, then modular multiplication can be performed, but the number of clock cycles is large and processing efficiency is low
Solution Approach 1:
The patent changes the representation parameter from standard binary to redundant binary representation, which allows for more efficient arithmetic operations. This parameter change enables the system to perform modular multiplication with fewer clock cycles by leveraging the properties of redundant representations to reduce computational steps
Solution Approach 2:
The patent implements a dynamic bit processing approach where the number of processing bits can be changed flexibly. The system processes bits from the least significant bit and can adaptively determine when to stop processing based on the intermediate results, allowing for dynamic adjustment of processing depth without requiring fixed circuit configurations for different bit lengths
2Productivity
If sequential processing is used in Montgomery multiplication, then the algorithm is simple to implement, but the number of operations increases and efficiency decreases
Solution Approach 1:
The patent segments the modular multiplication process into smaller operations by processing bits individually from the least significant bit. This segmentation allows the system to use simple adder circuits for each bit operation rather than requiring complex parallel architectures, achieving good efficiency without significant circuit complexity increase
Solution Approach 2:
Instead of processing bits from the most significant bit (conventional approach), the patent inverts the processing order and starts from the least significant bit. This inversion enables more efficient use of redundant binary representation and allows for earlier termination of processing when intermediate results become sufficient, reducing the total number of operations required
3Adaptability or versatility
If the number of processing bits is fixed to implement ZDN method, then the circuit design is simplified, but the adaptability to different bit lengths is reduced
Solution Approach 1:
The patent implements a dynamic bit processing approach where the number of processing bits can be changed flexibly. The system processes bits from the least significant bit and can adaptively determine when to stop processing based on the intermediate results, allowing for dynamic adjustment of processing depth without requiring fixed circuit configurations for different bit lengths
Solution Approach 2:
The patent creates a universal processing circuit that can handle different bit lengths and modular multiplication scenarios through a single unified architecture. The circuit uses generic adder components that can operate on varying numbers of bits, making the system adaptable to different cryptographic applications without requiring separate dedicated circuits for each bit length
Data Source
AI summary
According to one embodiment, a first shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of an intermediate result of a computation of Montgomery multiplication result z and calculates a first shift amount. A second shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of redundant-binary-represented integer x and calculates a second shift amount. An addition/subtraction unit calculates the intermediate result by adding/subtracting, with respect to the intermediate result which has been bit-shifted by the first shift amount, the integer p, and the integer y which has been bit-shifted by the second shift amount. An output unit outputs, as the Montgomery multiplication result z, the intermediate result when the sum of the first shift amounts is equal to the number of bits of the integer p.