Montgomery Modular Multiplication Pipelined Cell
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Solution Overview
Problem
Existing modular multiplication architectures in cryptology, particularly in FPGA and ASIC, face challenges in flexibility and efficiency, as they are either inflexible and resource-intensive or require high cycle counts due to fixed internal bus sizes, making them unsuitable for handling varying data sizes and operations like RSA and ECDSA efficiently.
Innovation Solution
A modular Montgomery multiplication device with a pipelined multiplier-adder architecture that uses larger base r (≥ 4) and splits operations into pipelined multiplication-addition and carry propagation, optimizing frequency and reducing cycle counts by using a single elementary cell with a higher base, thereby improving the time-area product.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional modular multiplication architectures are used, then hardware resources are sufficient for basic operations, but the architecture cannot efficiently process varying data sizes (flexibility is poor)
Solution Approach 1:
The patent implements a universal modular multiplication architecture that can process different data sizes (256-512 bits for ECDSA and 1024-4096 bits for RSA) using the same hardware structure. The multiplier-adder cell and pipelined architecture are designed to be size-agnostic, allowing the device to adapt to various cryptographic operations without requiring redesign or additional specialized hardware for each data size.
2Productivity
If small internal bus size is chosen, then hardware resources are reduced, but the number of cycles for modular multiplication increases significantly
Solution Approach 1:
The patent employs dynamic pipelining where the internal bus size and pipeline depth are optimized based on the specific operation being performed. The architecture can dynamically adjust the number of pipeline stages and bus width to balance between speed and resource usage, allowing faster execution when resources are available and efficient resource utilization when constrained.
Solution Approach 2:
The patent transitions from sequential processing to parallel processing by implementing a pipelined architecture with multiple pipeline stages. This dimensional change in time-space processing allows multiple operations to be performed simultaneously at different pipeline stages, dramatically reducing the total number of cycles required for modular multiplication while maintaining reasonable hardware resource usage.
3Productivity
If high base (r ≥ 4) is used, then the number of cycles for modular multiplication is reduced, but the complexity of the multiplier-adder increases
Solution Approach 1:
The patent segments the complex high-base multiplication operation into smaller, manageable stages within the pipelined architecture. Each pipeline stage handles a portion of the computation, breaking down the complex multiplier-adder operations into sequential steps that are easier to implement and control, thereby reducing the effective complexity while maintaining the performance benefits of high-base arithmetic.
Data Source
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AI summary
The invention relates to a modular multiplication device which is characterised in that it comprises at least one computation cell consisting of a multiplier/adder which comprises p pipeline register/logic pairs and which receives several figures to be added and multiplied, at least two outputs corresponding to the low order and the high order and an adder receiving the two outputs from the multiplier/adder, whereby p is selected such that the maximum frequency of the multiplier/adder is greater than or equal to the maximum frequency of the adder.