Montgomery Multiplier Circuit for Faster Modular Multiplication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing modular multiplication algorithms, particularly in number theory and cryptography, are slow due to the requirement of expensive division operations, which are inefficient and time-consuming.
Innovation Solution
A scalable Montgomery multiplier architecture that includes an initial processing element and multiple middle and final processing elements, configured to perform Montgomery multiplication efficiently by integrating multiplication and reduction steps, allowing parallel computation and reducing the number of computation cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If classical modular multiplication is used, then the operation can be performed, but the computation speed is slow due to expensive division operations
Solution Approach 1:
The patent changes the representation parameter of numbers from standard binary to Montgomery form (x*R mod N), where R is a radix typically a power of 2. This parameter transformation allows modular multiplication to be performed using only additions, subtractions, and bit shifts, eliminating the need for expensive division operations and significantly improving computation speed.
Solution Approach 2:
The patent substitutes the mechanical division operation with a combination of simpler operations: multiplication by pre-computed constants (R and R^-1 mod N), bit shifting, and conditional subtraction. This replacement of the division mechanism with lighter computational primitives directly addresses the speed problem while maintaining correctness.
2Productivity
If Montgomery multiplication is used, then computation speed improves, but the hardware architecture becomes more complex
Solution Approach 1:
The patent segments the Montgomery multiplication process into distinct functional blocks: initial processing element for conversion to Montgomery form, middle processing elements for the core multiplication iterations, and final processing elements for conversion back to standard form. This segmentation allows each block to be optimized independently and enables parallel processing of multiple bits simultaneously, improving productivity while managing hardware complexity through modular design.
Solution Approach 2:
The patent processes multiple bits of the operands in parallel by unrolling the iterative algorithm. Instead of processing one bit at a time sequentially, the hardware architecture computes multiple partial products simultaneously using array multipliers and combines them with proper alignment and addition, effectively adding a parallelism dimension to the computation.
3Loss of time
If division operations are used in modular multiplication, then the result is accurate, but the number of computation cycles increases
Solution Approach 1:
The patent performs preliminary actions by pre-computing the constants R (radix) and R^-1 mod N (modular inverse of R) before the actual Montgomery multiplication. These pre-computed values are stored in hardware registers and used throughout the computation, eliminating the need for repeated division operations during the main computation loop and significantly reducing the number of computation cycles required.
Data Source
AI summary
Montgomery multiplier architectures are provided. A circuit can include an initial processing element (PE) circuit configured to generate a first output including (i) a radix of a carry out and (ii) a radix of an intermediate result based on radixes of respective operands, a radix of an inverse of a modulus, and a radix of the modulus, middle PE circuits configured to generate a second output including (i) respective radixes of a Montgomery multiplication result and (ii) further respective radixes of a carry out on two consecutive clock cycles based on the first output, and a final PE circuit configured to generate further radixes of the Montgomery multiplication results on two consecutive, subsequent clock cycles based on the second output.