Montgomery Multiplication Integrated Circuit with Variable Word Widths
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Solution Overview
Problem
Montgomery multiplication, a fundamental operation in cryptographic algorithms, becomes significantly slower as the number of bits in the operands increases, limiting the speed of cryptographic systems based on large number operations.
Innovation Solution
The integrated circuit partitions the operands into words of different widths and uses a pipelined architecture with multiple processing elements to perform Montgomery multiplication, optimizing the use of multipliers and reducing idle clock cycles by cascading Montgomery multiplication units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of bits in the operands is increased to enhance security, then the security of the cryptographic system is improved, but the speed of Montgomery multiplication becomes significantly slower
Solution Approach 1:
The patent divides large operands into multiple smaller words (e.g., 32-bit words from a 1024-bit number), allowing the multiplication to be performed on manageable segments. This segmentation enables parallel processing and reduces the computational complexity of each individual multiplication operation, thereby maintaining security with large bit lengths while improving multiplication speed.
Solution Approach 2:
The patent introduces a hierarchical structure with outer loops iterating through multiplicand words and inner loops iterating through multiplier words. This multi-dimensional approach transforms a single large multiplication into multiple smaller multiplications organized in loops, enabling better utilization of hardware resources and improving overall computation speed.
2Device complexity
If uniform word widths are used for all operands, then the implementation is simpler, but the utilization of multipliers is not optimized and idle clock cycles increase
Solution Approach 1:
The patent assigns different word widths to different operands based on their specific requirements. For example, the multiplicand may be divided into 32-bit words while the multiplier is divided into 16-bit words, allowing each operand to be processed with the appropriate granularity. This local optimization maximizes multiplier utilization and reduces idle clock cycles.
Solution Approach 2:
The patent dynamically adjusts word widths and loop iteration counts based on the actual bit lengths of the input operands. This parameter adaptation allows the system to optimize performance for different operand sizes, improving multiplier utilization without requiring a completely different implementation for each case.
3Speed
If cascading Montgomery multiplication units is implemented to increase speed, then the latency is reduced and clock frequency is increased, but the device complexity increases
Solution Approach 1:
The patent cascades multiple Montgomery multiplication units to process different segments of the operands simultaneously. By merging these units in a pipeline architecture, the system achieves higher throughput and reduced latency. The unified interface and standardized word-width handling minimize the overhead introduced by cascading.
Solution Approach 2:
The patent employs dynamic control logic that adapts the operation of cascaded units based on the actual operand sizes. This dynamic behavior allows the system to activate only the necessary number of cascaded units for each multiplication task, reducing the effective complexity while maintaining the potential for high-speed operation when needed.
Data Source
AI summary
A system includes an integrated circuit configured to receive a multiplicand number, a multiplier number, and a modulus at one or more data inputs. The multiplicand number is partitioned into a plurality of multiplicand words. Each multiplicand word has a multiplicand word width. The multiplier number is partitioned into a plurality of multiplier words. Each multiplier word has a multiplier word width different from the multiplicand word width. A plurality of outer loop iterations of an outer loop is performed to iterate through the plurality of the multiplicand words. Each outer loop iteration of the outer loop includes a plurality of inner loop iterations of an inner loop performed to iterate through the plurality of the multiplier words. A Montgomery product of the multiplicand number and the multiplier number with respect to the modulus is determined.