Morph-Link Circuit for JESD 204 to UCIe Streaming Conversion
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Solution Overview
Problem
There is no standard streaming protocol defined for Universal Chiplet Interconnect Express (UCIe), leading to interoperability issues between streaming data chiplets from different vendors, and existing protocols like JESD 204 do not efficiently convert data to UCIe format for high-speed transmission without lowering data rates.
Innovation Solution
A morph-link circuit is used to separate control bits from data bits in JESD 204 formatted data, converting it to UCIe format for transmission over parallel interconnection lanes, allowing control information to be transmitted separately via a sideband channel, maintaining high data rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If packet-based protocols are used for streaming data transmission, then data can be transmitted with error handling and flow control, but protocol overhead increases, data rates decrease, and transmission gaps are required
Solution Approach 1:
The patent segments the data transmission into separate control signals and data streams. Control signals (including error handling and flow control) are transmitted on dedicated control lines, while data is transmitted on separate data lines. This segmentation eliminates protocol overhead from the data stream, maintaining high data rates while preserving reliability functions.
Solution Approach 2:
The patent introduces an intermediary conversion circuit that translates between packet-based protocols and the streamlined streaming protocol. This intermediary handles the complex error handling and flow control functions, allowing the data transmission path to remain simple and high-speed while reliability functions are preserved by the conversion layer.
2Adaptability or versatility
If protocol conversion circuits are added to convert between JESD 204 and UCIe formats, then interoperability between different vendors' chiplets is achieved, but device complexity increases
Solution Approach 1:
The patent extracts the protocol conversion functionality into a separate, dedicated conversion circuit module. This extracted module handles the complex protocol translation between JESD 204 and UCIe formats, while the rest of the system maintains simple, standardized interfaces. The complexity is contained and isolated in the conversion circuit, making the overall system more manageable and interoperable.
3Device complexity
If control bits are transmitted interleaved with data bits, then a single communication channel is used, but data rate is reduced due to overhead
Solution Approach 1:
The patent transitions from a single-dimensional serial transmission to a multi-dimensional parallel transmission structure. Control signals are transmitted on one set of lines while data is transmitted on separate parallel lines simultaneously. This dimensional separation allows both control and data to be transmitted concurrently without interfering with each other, eliminating the data rate reduction that would result from interleaving.
Data Source
AI summary
An example semiconductor device includes a first semiconductor die including a morph-link circuit and a first interface circuit. The morph-link circuit is configured to receive streaming data formatted in a first format according to a first protocol, the streaming data comprising a plurality of data bits in the first format and a plurality of control bits in the first format; and convert the streaming data to a second format according to a second protocol, including separating the plurality of control bits from the plurality of data bits. The morph-link circuit is further configured to transmit the streaming data in the second format to the first interface circuit, including transmitting the plurality of data bits in the second format via a first communication channel to the first interface circuit and transmitting control information corresponding to the plurality of control bits via a second communication channel to the first interface circuit.