MOS Antifuse Void-Accelerated Dielectric Breakdown
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Solution Overview
Problem
Monolithic MOS antifuse designs require higher program voltages due to intact gate dielectric, which hinders the scaling down of transistor dimensions and increases power consumption in integrated circuits.
Innovation Solution
Introducing a void or seam in the gate electrode of the MOS antifuse to accelerate dielectric breakdown, reducing the programming voltage by intentionally damaging the gate dielectric, allowing for lower antifuse program voltages through a process that exploits the seam formed during gate electrode deposition and etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the gate dielectric is kept intact in MOS antifuse, then the dielectric breakdown strength is maintained, but the program voltage becomes excessively high
Solution Approach 1:
A void or seam is intentionally created in the gate electrode during fabrication before the antifuse programming operation. This preliminary structural modification creates a predetermined weak point that accelerates dielectric breakdown during programming, allowing breakdown to occur at lower voltages than would be required for an intact gate electrode structure
Solution Approach 2:
The void or seam in the gate electrode, which represents a structural deficiency or imperfection, is converted into a beneficial feature that facilitates easier and lower-voltage dielectric breakdown. The intentional defect serves as a field emitter that concentrates electric field stress, transforming what would normally be a harmful imperfection into a useful mechanism for voltage reduction
2Use of energy by moving object
If the gate dielectric is intentionally damaged to lower breakdown voltage, then power consumption is reduced, but the manufacturing process becomes more complex
Solution Approach 1:
The void creation process is merged with existing gate electrode fabrication steps. The void or seam is formed as a byproduct or intentional feature during standard gate deposition and etching processes, combining the structural modification needed for voltage reduction with routine manufacturing operations rather than requiring separate additional processing steps
3Area of moving object
If transistor dimensions are scaled down, then device density increases, but the program voltage requirement increases
Solution Approach 1:
The gate electrode is designed with non-uniform properties - specifically, a void or seam is introduced at a localized position within the gate structure. This local modification creates a concentrated region of high electric field stress that initiates breakdown at lower voltages, compensating for the reduced overall device dimensions and enabling scaled-down transistors to maintain low programming voltage requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively lowers the dielectric breakdown voltage below typical thresholds, enabling more efficient and power-effective MOS antifuse operations while maintaining high dielectric breakdown strength in integrated circuits.
Implementation Method 1
Introducing a void or seam in the gate electrode of the MOS antifuse to accelerate dielectric breakdown
Data Source
AI summary
A MOS antifuse with an accelerated dielectric breakdown induced by a void or seam formed in the electrode. In some embodiments, the programming voltage at which a MOS antifuse undergoes dielectric breakdown is reduced through intentional damage to at least part of the MOS antifuse dielectric. In some embodiments, damage may be introduced during an etchback of an electrode material which has a seam formed during backfilling of the electrode material into an opening having a threshold aspect ratio. In further embodiments, a MOS antifuse bit-cell includes a MOS transistor and a MOS antifuse. The MOS transistor has a gate electrode that maintains a predetermined voltage threshold swing, while the MOS antifuse has a gate electrode with a void accelerated dielectric breakdown.