Analytical Model for Predicting Current Mismatch in MOS Arrays

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current mismatch in CMOS devices due to poly density gradient effects is not accurately predicted by conventional SPICE methodologies, leading to variations in device behavior and performance, especially in smaller technology nodes like 28 nm and 20 nm, which affects IC design and yield.

Innovation Solution

An analytical tool and method are provided to predict current mismatch in MOS arrays by modeling the impact of poly density gradient effects using standard deviations from central rows and columns, reducing the need for extensive silicon area and measurement points, and incorporating these variations into SPICE macro-models for more accurate IC design.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional SPICE methodologies are used to model current mismatch, then the modeling process is simple, but the prediction accuracy of current mismatch due to poly density gradient effects is poor

Engineering Contradiction:
Improveprediction accuracyVSAvoidmodeling complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent introduces new parameters (standard deviations of poly density gradient effects in x and y directions) to the existing SPICE model. These parameters quantify the variation effects that conventional models miss, allowing accurate prediction of current mismatch while maintaining compatibility with standard modeling frameworks.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent uses standard deviation as an intermediary parameter that bridges the gap between physical poly density gradient effects and electrical current mismatch. By measuring and modeling this intermediate statistical parameter, the system can predict final device behavior without directly simulating complex physical variations.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If extensive silicon area and measurement points are used for characterization, then the accuracy of current mismatch prediction improves, but the cost and time required for characterization increase

Engineering Contradiction:
Improvecharacterization accuracyVSAvoidcharacterization time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent measures standard deviations at only two central rows and two central columns of the MOS array, which is a partial sampling approach. This partial measurement strategy is sufficient to capture the poly density gradient effects and predict current mismatch across the entire array, avoiding the need for exhaustive measurement of all cells.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent divides the large MOS array into manageable segments (central rows and columns) for measurement. By focusing on these representative segments, the system can infer characteristics of the entire array without measuring every cell, thus reducing characterization time and resource requirements.

Inventive Principle:
Principle #1Segmentation

3Measurement precision

If standard deviations are determined for all cells in the MOS array, then the prediction accuracy improves, but the silicon area required for characterization increases

Engineering Contradiction:
Improveprediction accuracyVSAvoidsilicon area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent uses partial sampling by measuring only central rows and columns rather than all cells. This partial action provides sufficient statistical information to model poly density gradient effects across the entire array, achieving accurate predictions with minimal silicon area dedicated to characterization structures.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS8832619B2Analytical model for predicting current mismatch in metal oxide semiconductor arrays
Publication Date: 2014.09.09 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US8832619B2 patent drawing
  • US8832619B2 patent drawing
  • US8832619B2 patent drawing

AI summary

A system and method for designing integrated circuits and predicting current mismatch in a metal oxide semiconductor (MOS) array. A first subset of cells in the MOS array is selected and current measured for each of these cells. Standard deviation of current for each cell in the first subset of cells is determined with respect to current of a reference cell. Standard deviation of local variation can be determined using the determined standard deviation of current for one or more cells in the first subset. Standard deviations of variation induced by, for example, poly density gradient effects, in the x and/or y direction of the array can then be determined and current mismatch for any cell in the array determined therefrom.