Metal Oxide Semiconductor Array Substrate via Gray-Tone Mask Patterning
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Solution Overview
Problem
The manufacturing process of metal oxide semiconductor TFT array substrates requires multiple patterning processes, leading to high fabrication costs and instability in performance due to the need for an etch stop layer to prevent corrosion during electrode formation.
Innovation Solution
A method that reduces the number of patterning processes by forming a pattern layer including a pixel electrode, gate electrode, and gate line in one process, followed by sequential formation of a gate insulating layer, metal oxide semiconductor active layer, and etch stop layer, using gray-tone or half-tone masks to create via holes for electrode connections, thereby simplifying the process to three or four patterning processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple patterning processes are used to form the etch stop layer and metal oxide semiconductor active layer, then the etch stop layer can prevent corrosion of the metal oxide semiconductor active layer during electrode formation, but the fabrication cost increases and manufacturing complexity increases
Solution Approach 1:
The patent combines the formation of the etch stop layer and the metal oxide semiconductor active layer into a single patterning process. Multiple thin films (gate insulating layer, metal oxide semiconductor active layer, and etch stop layer) are formed sequentially, and a single gray-tone mask is used to pattern all three layers simultaneously, reducing the number of patterning steps from multiple separate processes to one integrated process.
Solution Approach 2:
The gray-tone mask serves multiple functions: it defines the patterns for the gate insulating layer, metal oxide semiconductor active layer, and etch stop layer all in one exposure step. This multi-functional approach allows a single masking operation to accomplish what would traditionally require multiple separate patterning processes.
2Reliability
If multiple patterning processes are used to manufacture the array substrate, then the etch stop layer can be formed to prevent corrosion, but the fabricating cost increases
Solution Approach 1:
The patent merges multiple patterning operations into one by using sequential film deposition (gate insulating layer, then metal oxide semiconductor active layer, then etch stop layer) followed by a single gray-tone mask exposure. This consolidation reduces the number of times photoresist must be applied, exposed, and developed, directly lowering material and processing costs.
Solution Approach 2:
The patent changes the exposure parameters by using a gray-tone mask with varying light transmission intensities. Different regions of the mask transmit different amounts of light, creating areas of full retention, partial retention, and full removal of photoresist in a single exposure step. This parameter variation allows one patterning process to achieve what would normally require multiple steps.
3Reliability
If multiple patterning processes are used to form the etch stop layer, then the metal oxide semiconductor active layer is protected from corrosion, but the production efficiency decreases
Solution Approach 1:
The patent combines multiple patterning steps into one by forming the gate insulating layer, metal oxide semiconductor active layer, and etch stop layer sequentially, then using a single gray-tone mask to pattern all three layers simultaneously. This eliminates the need for repeated photoresist application, exposure, and development cycles, significantly increasing manufacturing throughput.
Solution Approach 2:
The patent performs preliminary film formation by depositing the gate insulating layer, metal oxide semiconductor active layer, and etch stop layer in sequence before the patterning step. This preliminary preparation allows the subsequent single gray-tone mask exposure to pattern all three layers at once, rather than requiring separate patterning operations for each layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances production efficiency and reduces costs by minimizing the number of patterning processes, resulting in a more stable and cost-effective array substrate production.
Implementation Method 1
conducting an exposure of the substrate with the photoresist formed thereon by using a second gray-tone mask or a second half-tone mask, so as to form a photoresist fully-retained portion, a photoresist half-retained portion and a photoresist fully-removed portion after development
Data Source
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AI summary
An array substrate, a manufacturing method thereof, and a display device are provided, which are related to a display technology filed. The method includes: forming a pattern layer (201a) including a pixel electrode (20), and a pattern layer including a gate electrode (30) and a gate line on a base substrate (10) through one patterning process; on the substrate (10) with the pattern layer including the gate electrode (30) and the gate line formed thereon, forming a gate insulating layer (401), a pattern layer at least including a metal oxide semiconductor active layer (50) and a pattern layer at least including an etch stop layer (601) through one patterning process or two patterning processes; wherein, a first via hole (71) for exposing the pixel electrode (20) is formed over the pixel electrode (20); on the substrate (10) with the etch stop layer (601) formed thereon, forming a pattern layer including a source electrode (80a), a drain electrode (80b) and a data line through one patterning process; wherein, the source electrode (80a) and the drain electrode (80b) each contact a metal oxide semiconductor active layer (50), and the drain electrode (80a) is electrically connected to the pixel electrode (20) through the first via hole (71).