MOS-BJ ESD Device Reducing Turn-On Resistance
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Solution Overview
Problem
High-voltage electrostatic discharge (ESD) protection devices face challenges in achieving good ESD performance, particularly in smaller sizes, due to higher surface-bulk ratios, which lead to increased current density and electric field at surface junction regions, causing physical damage and unwanted latch-up, and require additional external ESD detection circuits to reduce trigger voltage.
Innovation Solution
A semiconductor device incorporating a metal-on-semiconductor (MOS) structure and a bipolar junction (BJ) structure formed in the substrate, where the MOS structure includes a drain, source, and channel regions, and the BJ structure includes an emitter, base, and collector region, with shared common regions, allowing for improved ESD current distribution and reduced turn-on resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the device size is reduced, then the surface-bulk ratio increases, but the ESD performance deteriorates due to higher current density and electric field at surface junction regions
Solution Approach 1:
The patent combines MOS and BJ structures into a single integrated device, allowing the ESD current to be handled by both structures simultaneously. This merging enables the device to maintain robust ESD protection in smaller form factors by distributing current handling across multiple mechanisms, thereby resolving the contradiction between reduced device size and maintained ESD performance.
Solution Approach 2:
The patent employs a composite structure integrating MOS (metal-oxide-semiconductor) and BJ (bipolar junction) structures. This composite approach leverages the strengths of both structures: the MOS structure provides high breakdown voltage while the BJ structure offers low on-state resistance and effective ESD current handling, enabling small devices to achieve excellent ESD performance.
2Reliability
If the on-state resistance is reduced, then the current density concentrates near the surface or drain, but physical damage occurs during ESD events
Solution Approach 1:
The patent segments the ESD current path into multiple regions handled by different structures. The MOS structure handles voltage blocking while the BJ structure handles current conduction through its emitter-base-collector path. This segmentation distributes the current density away from surface regions, preventing physical damage while maintaining low on-state resistance.
Solution Approach 2:
The patent introduces an intermediary mechanism where the BJ structure acts as a mediator between the high-voltage MOS structure and the ESD current. The bipolar junction provides a controlled current conduction path that prevents current concentration at sensitive surface regions, thereby protecting the device during ESD events while maintaining low resistance.
3Reliability
If the trigger voltage is reduced, then the ESD protection activates earlier, but additional external ESD detection circuits are required
Solution Approach 1:
The patent implements a self-service mechanism where the integrated MOS-BJ structure automatically triggers ESD protection based on internal voltage conditions. The bipolar junction's inherent characteristics enable automatic triggering when voltage exceeds a threshold, eliminating the need for external detection circuits while maintaining appropriate trigger voltage levels for timely protection.
4Reliability
If the holding voltage is reduced, then the device turns on easier during ESD, but latch-up occurs during normal operation due to noise or voltage spikes
Solution Approach 1:
The patent carefully optimizes the electrical parameters of both MOS and BJ structures, particularly the doping concentrations and geometry dimensions. By adjusting these parameters, the holding voltage is set to an optimal level that enables easy ESD activation while maintaining stability against spurious triggering from noise or voltage spikes, thus preventing latch-up during normal operation.
Data Source
AI summary
A semiconductor device formed in a substrate, including a first region, a second region formed over the first region, a third region, a fourth region formed over the third region, and a fifth region formed over the first region and contacting the second region. The first, second, and fourth regions have a first-type conductivity, and constitute drain region, drain electrode, and source region of a metal-on-semiconductor (MOS) structure. The second region has a higher doping level than the first region. The third region has a second-type conductivity and constitutes channel and body regions of the MOS structure. The fifth region has the second-type conductivity and constitutes an emitter region of a bipolar junction (BJ) structure. The second and third regions constitute base and collector regions of the BJ structure.