MOS Transistor BTI Mitigation Using Delayed Control Signals

The patent applies periodic action by introducing delay circuits that periodically toggle between delaying operation signals and flag signals. This periodic switching creates alternating stress conditions on PMOS and NMOS transistors, preventing continuous degradation in one direction. The delay circuits switch between two states: delaying the operation signal to suppress NBTI in PMOS, and delaying the flag signal to suppress PBTI in NMOS, thereby maintaining threshold voltage stability over time.

The patent changes the timing parameters of control signals by introducing predetermined delays. The delay circuits modify the temporal characteristics of operation signals and flag signals, creating time-shifted versions of these signals. This parameter change in signal timing allows the transistors to experience alternating stress conditions, which counteracts the cumulative threshold voltage shift that would occur with continuous operation in a single state.

The delay circuits in the patent serve multiple functions: they delay operation signals to suppress NBTI in PMOS transistors, delay flag signals to suppress PBTI in NMOS transistors, and generate controlled timing signals for various circuit operations. By making the delay circuits multi-functional, the patent reduces the need for separate dedicated circuits for each function, thereby limiting the increase in overall device complexity while achieving comprehensive BTI suppression.

The delay circuits act as intermediary elements between the control logic and the MOS transistors. Rather than modifying the transistor structures themselves or adding complex protection circuits directly to each transistor, the patent introduces delay circuits as mediators that manipulate control signals to indirectly protect the transistors from BTI degradation. This intermediary approach provides a relatively simple solution compared to direct transistor modification.