MOS Bulk Bias Switching for Low-Leakage IO Circuits
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Solution Overview
Problem
In advanced semiconductor technology nodes, such as 40 nm, the leakage current in MOS transistors becomes unacceptable, necessitating new mechanisms to control and reduce leakage currents effectively.
Innovation Solution
The bulks of MOS transistors in peripheral circuits of an embedded DRAM are configured to selectively receive either a regular operational voltage or a back bias voltage, with charge pumps generating these back bias voltages to reduce leakage current in standby, deep power down, and power down modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the bulks of MOS transistors are connected directly to regular voltage sources (VSS for NMOS, VDD for PMOS), then the circuit operation is simple and straightforward, but leakage current becomes unacceptable in advanced semiconductor nodes such as 40 nm
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the bulk voltage potential of MOS transistors. Instead of connecting bulks to fixed regular voltage sources, the invention introduces variable back-bias voltages (VBN for NMOS, VBP for PMOS) that can be adjusted to optimize leakage current. This changes the electrical parameter (bulk potential) to control the harmful leakage effect while maintaining transistor functionality.
Solution Approach 2:
The patent introduces intermediary components including bulk voltage generation circuits and switching networks that mediate between the regular power sources and the transistor bulks. These intermediaries actively manage the bulk potentials to reduce leakage current, acting as a control layer between the simple power connection and the transistor devices.
2Object-generated harmful factors
If back bias voltages are applied to reduce leakage current, then leakage current is reduced effectively, but the device complexity increases due to additional charge pumps and voltage generation circuits
Solution Approach 1:
The patent implements multi-functionality by designing bulk voltage generation circuits that serve multiple purposes: generating back-bias voltages for leakage reduction, providing switching control for different operational modes, and integrating with existing power supply networks. The same circuit infrastructure supports both leakage reduction and normal operation, reducing the net complexity increase.
Solution Approach 2:
The invention merges the bulk voltage generation functionality with existing power supply circuits. Rather than adding completely separate systems, the patent integrates charge pumps and voltage generation logic into the existing power distribution network, combining multiple functions into shared circuitry to minimize overall device complexity.
Data Source
AI summary
A circuit includes an input/output (IO) circuit, a first node configured to have a first voltage level, a second node configured to have a second voltage level, a third node, and a switching circuit. The IO circuit has a set of transistors, and the third node is coupled to bulks of the set of transistors. The switching circuit is configured to couple the first node to the third node when the IO circuit is operated in an active mode; and couple the second node to the third node when the IO circuit is operated in an inactive mode. The first voltage level causes the set of transistors to have a first threshold voltage, the second voltage level causes the set of transistors to have a second threshold voltage, and an absolute value of the second threshold voltage is greater than that of the first threshold voltage.