MOS Variable Capacitance Network for Stable PLL Tuning
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Solution Overview
Problem
Existing variable capacitance components in phase locked loops suffer from high costs, manufacturing variability, limited operating bandwidth, and inaccuracies due to the use of complex and sensitive components, which can introduce noise and sensitivity to temperature, process, and voltage variations.
Innovation Solution
A variable capacitance circuit using Metal Oxide Semiconductor (MOS) transistors or other semiconductor devices to switch capacitors in and out, configured in a parallel network with offset bias voltages, providing a wide voltage range and immunity to temperature, process, and voltage variances, and integrated into phase locked loop circuits to produce a stable voltage reference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional variable capacitance components (varactors, variacap diodes) are used in phase locked loops, then capacitance adjustment capability is provided, but manufacturing variability and sensitivity to temperature, process, and voltage variations increase
Solution Approach 1:
The patent replaces traditional mechanical/electronic variable capacitance components (varactors, variacap diodes) with a digital capacitor array controlled by logic circuitry. Instead of using voltage-controlled capacitance adjustment, the system uses binary-weighted capacitor switches controlled by digital signals, eliminating the manufacturing variability and environmental sensitivity associated with traditional variable capacitance components.
Solution Approach 2:
The patent creates a digital representation of capacitance values using binary-weighted capacitor arrays. Each capacitor in the array represents a binary weight (1, 2, 4, 8, etc.), and by switching combinations of these capacitors, any desired capacitance value can be synthesized. This digital copying approach provides precise, repeatable capacitance settings不受manufacturing variations.
2Adaptability or versatility
If digital phase locked loop circuits use multiple fixed-value capacitors to adjust capacitance, then capacitance range is achieved, but design time, surface area, and component count increase
Solution Approach 1:
The patent segments the total capacitance range into binary-weighted portions using individual capacitor elements arranged in a structured array. Each capacitor represents a specific binary weight, and by selectively switching these segments, the full capacitance range is achieved with minimal components. This segmentation allows systematic coverage of the capacitance range while maintaining low component count.
Solution Approach 2:
The patent implements dynamic capacitance adjustment through binary-weighted capacitor switching controlled by digital logic. Instead of using multiple large fixed capacitors, the system dynamically selects and combines smaller capacitors based on the desired capacitance value, enabling flexible capacitance range adjustment with reduced component count and optimized layout.
3Adaptability or versatility
If digital phase locked loop circuits switch fixed-value capacitors to adjust capacitance, then capacitance variation is achieved, but noise increases due to inability to smoothly adjust
Solution Approach 1:
The patent uses binary-weighted capacitor arrays where only the necessary portion of capacitors are switched at any given time to achieve the desired capacitance value. This partial switching approach minimizes transient effects and noise compared to switching all capacitors, while still providing full capacitance variation range. The systematic binary weighting ensures smooth transitions with minimal disturbance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces component complexity and cost, enhances accuracy, and improves noise immunity by maintaining constant charge pump current pulse magnitude and low pass filter resistance sensitivity, resulting in a phase locked loop circuit that is less sensitive to manufacturing and environmental variations.
Implementation Method 1
A variable capacitance circuit may operate a Metal Oxide Semiconductor (MOS) transistor or other semiconductor device to switch a capacitor in and out
Data Source
AI summary
A variable capacitance circuit may operate a Metal Oxide Semiconductor (MOS) transistor or other semiconductor device to switch a capacitor in and out. Several circuits may be combined in a parallel network having offset bias voltages, such that the combined network may produce a variable capacitance over a large voltage range. The variable capacitance circuit may be incorporated into a phase locked loop (PLL) circuit where similar devices may be configured to produce a voltage reference as part of the PLL circuitry. Such a circuit may be immune to temperature, process, or voltage variances, since the current pulse magnitude times the low pass filter resistance times the sensitivity of a controlled voltage oscillator can be held constant.