MOS Capacitor Structure for Low-Cost CMOS Image Sensor Circuits
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Solution Overview
Problem
Current metal-insulator-metal (MIM) capacitors used in CMOS image sensor circuits are costly due to the need for additional photomasks, are sensitive to back-end process variations, occupy more chip area, and require complex back-end metal routing.
Innovation Solution
A metal-oxide-semiconductor (MOS) capacitor structure is developed, comprising a substrate with an ion well and counter doping region, a capacitor dielectric layer, and doping regions, which are compatible with the front-end manufacturing process, reducing costs and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MIM capacitors are used in CMOS image sensor circuits, then capacitance function is achieved, but manufacturing cost increases due to additional photomasks
Solution Approach 1:
The patent merges the capacitor structure with the existing CMOS transistor structure by using the same doped regions (source and drain) for both functions. The gate electrode serves as one plate of the capacitor while the doped region serves as the other plate, eliminating the need for separate MIM capacitor structures and additional photomasks.
Solution Approach 2:
The patent makes the transistor structure multi-functional by enabling it to serve both as a switching device and as a capacitor. The gate electrode and doped region combination provides capacitance functionality alongside the transistor's primary switching function, reducing overall device count and manufacturing complexity.
2Reliability
If MIM capacitors are used, then capacitance is achieved, but chip area occupation increases
Solution Approach 1:
The patent combines the capacitor function within the footprint of the transistor structure. By using the gate electrode and doped region that are already present in the CMOS circuit, the capacitor occupies the same area as the transistor rather than requiring additional dedicated space, thereby increasing circuit density.
3Reliability
If MIM capacitors are used, then capacitance function is provided, but back-end process variation sensitivity increases
Solution Approach 1:
The patent uses the transistor's gate electrode and doped regions to create the capacitor, making it part of the front-end CMOS fabrication process rather than a separate back-end metal process. This integration reduces sensitivity to back-end process variations since the capacitor structure is formed during the standard transistor fabrication sequence.
4Reliability
If MIM capacitors are used, then capacitance is achieved, but device complexity increases due to additional metal routing
Solution Approach 1:
The patent merges the capacitor connections with the existing transistor terminals. The gate electrode and doped region are already connected to the circuit through standard transistor routing, so the capacitor inherits these connections without requiring additional metal layers or routing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The MOS capacitor provides stable voltage-independent capacitance, improved threshold voltage, and higher circuit density with lower manufacturing costs, while the core oxide layer increases capacitance value.
Implementation Method 1
an ion well having a first conductivity type in the substrate; a counter doping region having a second conductivity type in the ion well within the capacitor forming region
Implementation Method 2
a capacitor dielectric layer on the ion well within the capacitor forming region; a gate electrode on the capacitor dielectric layer
Data Source
AI summary
A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.