MOS Capacitor Well Structure for Noise Filtering and Leakage Control
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Solution Overview
Problem
Current semiconductor devices, particularly those of smaller sizes, experience current leakage due to noise signals, especially high-frequency noise, leading to reduced product performance and lifetime, as traditional filter devices fail to effectively mitigate this issue over time.
Innovation Solution
A metal-oxide-semiconductor (MOS) capacitor with a lower electrode featuring heavy dopants like arsenic, which maintains a consistent profile during manufacturing and annealing, and additional doping regions with different conductivity types to prevent leakage, along with increased isolation depth to prevent lateral leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If traditional filter devices are used to filter noise signals, then noise filtration is provided, but current leakage occurs after extensive usage time
Solution Approach 1:
The patent divides the filtering function into multiple stages by introducing a MOS capacitor structure with separate doping regions (first doping region with first conductivity type, second doping region with second conductivity type) that work together to filter noise signals while preventing current leakage through coordinated operation of isolated regions
Solution Approach 2:
The patent introduces an isolation structure as an intermediary element between the first and second doping regions. This isolation prevents direct electrical interaction that would cause current leakage while allowing both regions to contribute to noise filtration, effectively mediating between the conflicting requirements of noise filtering and leakage prevention
2Volume of moving object
If device size is reduced, then product size is minimized, but current leakage frequently occurs
Solution Approach 1:
The patent applies local quality by creating doping regions with different conductivity types in specific locations within the semiconductor structure. The first doping region has first conductivity type and the second doping region has second conductivity type, with each region having optimized local properties to prevent current leakage while maintaining compact overall device size
Solution Approach 2:
The patent addresses current leakage in miniaturized devices by introducing vertical dimensionality through the isolation structure that separates doping regions at different depths or positions. This dimensional separation prevents lateral current leakage paths while maintaining the compact footprint required for small device size
3Ease of manufacture
If doping region profile changes during annealing, then manufacturing process is simplified, but current leakage increases
Solution Approach 1:
The patent applies preliminary action by forming the isolation structure and doping regions in a specific sequence before annealing. The isolation is established and doping regions are defined with their respective conductivity types prior to the annealing process, so that when annealing occurs, the pre-established isolation structure prevents dopant diffusion that would cause current leakage, while still allowing the annealing to activate and optimize the electrical properties of the doping regions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The MOS capacitor effectively reduces current leakage, enhancing product performance and extending the product lifetime by maintaining a consistent doping region profile and utilizing additional doping regions to prevent leakage, thus improving noise filtration in semiconductor devices.
Implementation Method 1
a lower electrode, disposed at the first surface and comprising a portion of the substrate, wherein the second electrode includes heavy dopants
Implementation Method 2
an isolation, disposed in the substrate and surrounding the first well region, wherein a depth of the isolation is substantially greater than or equal to a depth of the first well region from a first surface of the substrate
Data Source
AI summary
A semiconductor structure including a substrate, a first well region, a second well region, an isolation, a gate structure, and a dielectric layer is provided. The first well region is disposed in the substrate, wherein a dopant of the first well region includes arsenic. The second well region is disposed in the substrate under the first well region, wherein the second well region has a conductivity type different from that of the first doping region. The isolation is disposed in the substrate and surrounds the first well region, wherein a depth of the isolation is substantially greater than or equal to a depth of the first well region from a first surface of the substrate. The gate structure are disposed sequentially over the substrate and overlaps the first well region. A method of forming the semiconductor structure is also provided.