MOS Capacitor Linearity via Segmented Back-to-Back Branches
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Solution Overview
Problem
MOS capacitors exhibit non-linearity due to capacitance variation with voltage, limiting their suitability for applications requiring high linearity, especially during transitions between depletion and oxide regions, and existing techniques provide only limited improvement.
Innovation Solution
The MOS capacitor apparatus is designed with a main branch and auxiliary branches, featuring back-to-back capacitor configurations, large offset biasing, and specific capacitance ratios to force operation in either the oxide or depletion region, reducing capacitance variation and enhancing linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MOS capacitor is used to save circuit area, then capacitance density is improved, but linearity deteriorates due to capacitance variation with voltage
Solution Approach 1:
The patent divides the capacitor structure into multiple segments: a first capacitor with first and second plates, a second capacitor with third and fourth plates, and a third capacitor with fifth and sixth plates. These capacitors are connected in series with specific polarity arrangements to cancel out non-linear capacitance variations while maintaining high capacitance density in a compact area.
2Reliability
If multiple stages are added together in multi-tan technique, then capacitor variation is reduced, but device complexity increases
Solution Approach 1:
The patent merges multiple capacitor functions into a single integrated structure where the first, second, and third capacitors are connected in series within one apparatus. This combination achieves capacitance variation reduction through complementary non-linear characteristics without requiring separate multi-stage circuits, thereby reducing overall device complexity while maintaining capacitance stability.
3Adaptability or versatility
If MOS capacitor operates during transition between depletion and oxide region, then voltage swing range is extended, but linearity deteriorates due to capacitance variation
Solution Approach 1:
The patent employs asymmetric capacitor configurations where the first capacitor has different plate arrangements compared to the second and third capacitors. The first capacitor includes a first plate and second plate with specific doping regions, while the second capacitor has a third plate and fourth plate with complementary characteristics. This asymmetry ensures that when voltage swings across different regions, the non-linear capacitance variations of individual capacitors cancel each other out, maintaining linearity across extended voltage ranges.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves improved linearity and reduced capacitance variation across a wider voltage range, allowing for more efficient use of circuit area and increased suitability in applications with large voltage swings.
Implementation Method 1
MOS capacitors are used in many applications, such as in analog filters. MOS capacitors are much denser than metal-on-metal (MOM) capacitors and therefore can be used in place of MOM capacitors to save circuit area.
Implementation Method 2
This nonlinearity mainly happens during MOS capacitor transition from depletion to oxide region and vice versa when capacitor voltage varies.
Implementation Method 3
This nonlinearity mainly happens during MOS capacitor transition from depletion to oxide region and vice versa when capacitor voltage varies.
Data Source
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AI summary
A MOS capacitor with improved linearity is disclosed. In an exemplary embodiment, an apparatus includes a main branch comprising a first signal path having a first capacitor pair connected in series with reversed polarities and a second signal path having a second capacitor pair connected in series with reversed polarities, the first and second signal paths connected in parallel. The apparatus also includes an auxiliary branch comprising at least one signal path having at least one capacitor pair connected in series with reversed polarities and connected in parallel with the main branch. In an exemplary embodiment, the capacitors are MOS capacitors.