Stacked MOS Capacitor Electrode Layout for Low Parasitic Impedance
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Solution Overview
Problem
Existing electronic components with MOS capacitors suffer from high parasitic impedance, including parasitic capacitance, resistance, and inductance, which affect the performance of internal voltage generating circuits in semiconductor memory systems.
Innovation Solution
The design incorporates a semiconductor substrate with a dielectric layer and internal electrodes, where extended electrodes are strategically positioned to reduce parasitic impedance, using a silicon semiconductor substrate and thermal oxide film as the dielectric, and metal films for electrodes to minimize parasitic components, thereby configuring a capacitor with ideal electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a MOS capacitor is provided between the gate and N-type well across the gate insulating film, then the capacitor can be integrated into the semiconductor substrate, but parasitic impedance (capacitance, resistance, and inductance) is generated in the wiring layer and between layers
Solution Approach 1:
The patent transitions from a planar capacitor structure to a three-dimensional stacked structure where the first and second internal electrodes are positioned at different vertical levels within the insulator layer. This dimensional change allows the electrodes to be electrically connected while minimizing parasitic impedance by reducing the area of overlapping conductive layers, thereby decreasing parasitic capacitance between the wiring layer and semiconductor substrate.
Solution Approach 2:
The patent employs a nested configuration where the second extended electrode is positioned inside the second internal electrode when viewed from above. This nested arrangement optimizes the electrical connection path and minimizes the loop area for current flow, thereby reducing parasitic inductance and resistance while maintaining effective capacitance.
2Ease of operation
If wiring layers are used to connect the capacitor electrodes, then electrical connections can be established, but parasitic resistance and inductance components are generated in the wiring layer itself
Solution Approach 1:
The patent extracts the electrode connection function from the traditional wiring layer by directly forming internal electrodes (first and second internal electrodes) within the insulator layer. This separation eliminates the need for separate wiring layers to connect capacitor electrodes, thereby removing the parasitic resistance and inductance that would be introduced by additional wiring layers and contact holes.
Solution Approach 2:
The patent merges the electrode formation and connection functions into a single integrated structure where the internal electrodes are directly formed in the insulator layer and extend to the surface. This consolidation eliminates intermediate connection structures and reduces the overall current path length, minimizing parasitic resistance and inductance while maintaining electrical connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in a low-parasitic impedance capacitor, enhancing circuit performance in high-frequency applications by reducing parasitic capacitance, resistance, and inductance, leading to a low-loss circuit with improved design characteristics.
Implementation Method 1
a dielectric layer adjacent the surface of the semiconductor substrate
Data Source
AI summary
An electronic component including: a semiconductor substrate; a dielectric layer adjacent a surface of the semiconductor substrate; a first internal electrode electrically connected to the semiconductor substrate; a second internal electrode adjacent a surface of the dielectric layer; an insulator layer adjacent the surface of the semiconductor substrate and covering the first internal electrode and the second internal electrode; a first extended electrode electrically connected to the first internal electrode; a second extended electrode electrically connected to the second internal electrode, wherein when viewed in a direction perpendicular to a plane of the semiconductor substrate, the second extended electrode is inside the second internal electrode; a first external electrode electrically connected to the first extended electrode; and a second external electrode electrically connected to the second extended electrode.