MOS Capacitor Memory Cell for Longer Data Retention
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Solution Overview
Problem
Current random access memories, such as SRAM and DRAM, face issues with excessive cell size and short data retention times due to the use of six transistors in SRAM cells and destructive readout in DRAM, leading to reduced density and frequent refresh operations.
Innovation Solution
A memory cell design incorporating a write transistor, a read transistor, and a metal oxide semiconductor (MOS) capacitor with a synchronization pulse signal applied to the capacitor, allowing for efficient data storage and retrieval while reducing cell size through shared components and optimized voltage control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If six transistors are used in SRAM cells, then reliability is improved, but area increases excessively
Solution Approach 1:
The patent merges the capacitor structure into the transistor gate, creating a unified device where the gate electrode serves dual purposes as both the transistor gate and the capacitor electrode. This integration eliminates the need for separate capacitor structures, thereby reducing cell area while maintaining data retention functionality.
Solution Approach 2:
The gate electrode is designed to perform multiple functions: it acts as the control gate for the transistor during read/write operations and simultaneously serves as one of the capacitor electrodes for data storage. This multi-functionality reduces the total component count and cell area while preserving the reliability benefits of traditional SRAM designs.
2Area of moving object
If DRAM cells are used, then area is reduced, but data retention time becomes short requiring frequent refresh
Solution Approach 1:
By integrating the capacitor function into the transistor gate structure, the patent creates a hybrid device that combines the compactness of DRAM with enhanced data retention characteristics. The merged structure allows for larger effective capacitance within a smaller area compared to traditional DRAM, extending data retention time without sacrificing area efficiency.
Solution Approach 2:
The patent employs a composite structure where the gate electrode material and capacitor dielectric are integrated in a unified device architecture. This composite design enables the cell to achieve both the small area of DRAM and the longer data retention time characteristic of devices with larger capacitance, effectively resolving the contradiction between area and retention time.
3Ease of operation
If traditional DRAM readout is performed, then read operation is simple, but data is destroyed requiring refresh
Solution Approach 1:
The integrated gate-capacitor structure enables a read operation mechanism where the transistor gate controls data flow to the bit line while the capacitor maintains the stored charge. This merging allows for non-destructive or partially non-destructive readout, as the capacitor can replenish charge lost during reading, reducing the need for immediate refresh operations while keeping the read process relatively simple.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed memory cell design enhances data retention time and reduces the need for frequent refresh operations, improving memory density and operational efficiency compared to traditional SRAM and DRAM technologies.
Implementation Method 1
a metal oxide semiconductor (MOS) capacitor including a gate electrode coupled to the storage node
Data Source
AI summary
A memory cell includes a metal oxide semiconductor (MOS) capacitor including a gate coupled to a storage node and an electrode coupled to a synchronization control line. The MOS capacitor adds a coupling voltage to the gate based on a change in voltage on the synchronization control line. The coupling voltage may maintain the storage node within a predetermined range.